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@@ -150,6 +150,20 @@ dense arch first; **hard-error at load** if combined with DCA / rolling-KV /
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  sparse / MTP until each sizing loop is made eff-aware (explicit follow-ups). This
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  prevents silent under-allocation, which would corrupt rather than error.
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  ## 7. Per-architecture scope
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  ### Phase 1 — Qwen3.5 / Qwen3.6 **dense** (MVP target)
 
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  sparse / MTP until each sizing loop is made eff-aware (explicit follow-ups). This
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  prevents silent under-allocation, which would corrupt rather than error.
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+ > **STATUS UPDATE (RYS-12 / #667, 2026-07-13 — SUPERSEDES the MVP rule above):**
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+ > the DCA / rolling-KV-residency / sparse-attn guards are **LIFTED**. The three
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+ > residency sizing loops (`opencoti_compute_auto_gpu_heads_frac` /
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+ > `_resident_window_cells` / `_auto_select_kv_tier`) iterate the EFFECTIVE plan
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+ > (eff→src), the DCA build path maps `eff→src` for `is_swa`, and sparse-attn
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+ > alloc lives inside the eff-iteration loop (authoritative comment:
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+ > `src/llama-context.cpp` ~line 268). RYS now composes with DCA, rolling-KV
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+ > window/spill, sparse-attn, quant-KV, and MTP (draft context runs the plain
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+ > base stack — bug-2171 — target keeps RYS; lossless). RYS × rolling-KV window
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+ > spill was live-validated 2026-07-14 on the qwen35moe hybrid (bug-2172 gate:
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+ > 44 eff layers + 256/40704 window+tail, needle recovered, no assert). The
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+ > remaining hard-errors are: unsupported archs (RYS-4) and malformed/boundary
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+ > plans (parse validation); boundary-band plans get an advisory WARN.
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+
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  ## 7. Per-architecture scope
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  ### Phase 1 — Qwen3.5 / Qwen3.6 **dense** (MVP target)