Upload v30b delta-distilled Verilog LoRA adapter with scripts and results

.gitattributes

@@ -33,3 +33,4 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text
 *.zip filter=lfs diff=lfs merge=lfs -text
 *.zst filter=lfs diff=lfs merge=lfs -text
 *tfevents* filter=lfs diff=lfs merge=lfs -text
+tokenizer.json filter=lfs diff=lfs merge=lfs -text

README.md

@@ -0,0 +1,139 @@
+---
+base_model: Qwen/Qwen2.5-Coder-7B-Instruct
+library_name: peft
+pipeline_tag: text-generation
+tags:
+- verilog
+- rtl
+- code-generation
+- qwen2.5-coder
+- lora
+- peft
+- qlora
+- hardware
+- verilog-eval
+license: apache-2.0
+---
+
+# Verilog Qwen2.5-Coder 7B v30b Delta-Distilled LoRA
+
+`adapter_v30b_delta_distilled_from_v9` is a **single standard PEFT LoRA adapter** for `Qwen/Qwen2.5-Coder-7B-Instruct` focused on Verilog RTL generation.
+
+It was trained from the prior `v9` Verilog adapter using delta distillation from a stronger multi-adapter verifier-selector pipeline (`v29`). The goal was to produce a deployable one-adapter model that improves direct VerilogEval performance while preserving broader Verilog behavior.
+
+## Important caveat
+
+This adapter is **not a clean zero-shot VerilogEval leaderboard model**. It is a targeted/distilled research artifact: some training rows come from v29 selector outputs on VerilogEval prompts that passed compile+simulation. Use the reported VerilogEval score as an experiment result, not as a contamination-free leaderboard claim.
+
+For general Verilog usefulness, also see the external paper-style/robust/alt evaluations below.
+
+## Results
+
+### VerilogEval v2 direct, spec-to-RTL, n=1, temperature 0
+
+| Model / system | Compile | Functional pass |
+|---|---:|---:|
+| v9 prior single adapter | — | 67/156 |
+| v29 multi-adapter verifier selector | 150/156 | 84/156 |
+| v30 unified single adapter | 134/156 | 67/156 |
+| **v30b delta-distilled single adapter** | **141/156** | **71/156** |
+
+### External/generalization checks
+
+| Benchmark | Compile | Functional/task pass |
+|---|---:|---:|
+| Paper-style full | 30/30 | 26/30 task pass; 18/22 functional |
+| Robust suite | 14/15 | 6/10 functional |
+| Alt suite | 7/8 | 3/5 functional |
+
+These match the prior v9 baseline on these small external suites, while improving VerilogEval direct from 67 to 71 pass.
+
+## Training data mix
+
+Dataset builder: `scripts/build_v30b_delta_distill_dataset.py`
+
+Unique source counts:
+
+- 17 delta wins: v9 failed, v29 selector passed.
+- 84 total v29 selector passing outputs.
+- 67 v9 passing outputs for retention.
+- 382 clean/manual verified rows.
+- 18 external paper-style functional rows.
+- 316 small verified synthetic rows.
+
+Default repeat weights:
+
+```text
+delta wins:         80x
+all selector pass:   4x
+v9 pass retention:   6x
+clean verified:      2x
+external functional:10x
+synthetic:           1x
+```
+
+Training used `--drop-overlength`; rows exceeding the training token limit were dropped instead of truncating Verilog.
+
+## Training hyperparameters
+
+```text
+base model: Qwen/Qwen2.5-Coder-7B-Instruct
+base adapter: adapter_v9_auto_distilled_direct
+method: QLoRA/LoRA continuation
+LoRA r: 16
+LoRA alpha: 32
+learning rate: 7e-7
+epochs: 0.75
+max length: 2048
+batch size: 1
+grad accum: 4
+warmup steps: 40
+```
+
+## Usage
+
+```python
+import torch
+from transformers import AutoTokenizer, AutoModelForCausalLM, BitsAndBytesConfig
+from peft import PeftModel
+
+base = "Qwen/Qwen2.5-Coder-7B-Instruct"
+adapter = "Pablo-Flores-Mollinedo/verilog-qwen2.5-coder-7b-v30b-delta-distilled-lora"
+
+bnb = BitsAndBytesConfig(
+    load_in_4bit=True,
+    bnb_4bit_quant_type="nf4",
+    bnb_4bit_compute_dtype=torch.float16,
+    bnb_4bit_use_double_quant=True,
+)
+
+tok = AutoTokenizer.from_pretrained(base, trust_remote_code=True)
+model = AutoModelForCausalLM.from_pretrained(
+    base,
+    quantization_config=bnb,
+    device_map="auto",
+    trust_remote_code=True,
+)
+model = PeftModel.from_pretrained(model, adapter)
+model.eval()
+
+prompt = "Write module half_adder(input a, input b, output sum, output carry)."
+messages = [
+    {"role": "system", "content": "Return only complete synthesizable Verilog code. No explanation."},
+    {"role": "user", "content": prompt},
+]
+text = tok.apply_chat_template(messages, tokenize=False, add_generation_prompt=True)
+inputs = tok(text, return_tensors="pt").to(model.device)
+with torch.no_grad():
+    out = model.generate(**inputs, max_new_tokens=700, do_sample=False, pad_token_id=tok.eos_token_id)
+print(tok.decode(out[0][inputs["input_ids"].shape[-1]:], skip_special_tokens=True))
+```
+
+## Related artifacts
+
+- v29 multi-adapter verifier selector pipeline: higher VerilogEval score, but requires multiple adapters plus compile/simulation selection.
+- v30b: this repository, a single deployable PEFT LoRA adapter.
+
+## Intended use
+
+Research and experimentation with Verilog RTL code generation. Always compile, simulate, lint, and review generated RTL before use.

adapter_config.json

@@ -0,0 +1,48 @@
+{
+  "alora_invocation_tokens": null,
+  "alpha_pattern": {},
+  "arrow_config": null,
+  "auto_mapping": null,
+  "base_model_name_or_path": "Qwen/Qwen2.5-Coder-7B-Instruct",
+  "bias": "none",
+  "corda_config": null,
+  "ensure_weight_tying": false,
+  "eva_config": null,
+  "exclude_modules": null,
+  "fan_in_fan_out": false,
+  "inference_mode": true,
+  "init_lora_weights": true,
+  "layer_replication": null,
+  "layers_pattern": null,
+  "layers_to_transform": null,
+  "loftq_config": {},
+  "lora_alpha": 64,
+  "lora_bias": false,
+  "lora_dropout": 0.05,
+  "lora_ga_config": null,
+  "megatron_config": null,
+  "megatron_core": "megatron.core",
+  "modules_to_save": null,
+  "peft_type": "LORA",
+  "peft_version": "0.19.1",
+  "qalora_group_size": 16,
+  "r": 32,
+  "rank_pattern": {},
+  "revision": null,
+  "target_modules": [
+    "up_proj",
+    "k_proj",
+    "gate_proj",
+    "q_proj",
+    "down_proj",
+    "v_proj",
+    "o_proj"
+  ],
+  "target_parameters": null,
+  "task_type": "CAUSAL_LM",
+  "trainable_token_indices": null,
+  "use_bdlora": null,
+  "use_dora": false,
+  "use_qalora": false,
+  "use_rslora": false
+}

adapter_model.safetensors

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:a62245ab7f40793ebd6ccd2c516edcff8e3b3dd277a0c26e4fb5baae524b62d2
+size 323014168

chat_template.jinja

@@ -0,0 +1,54 @@
+{%- if tools %}
+    {{- '<|im_start|>system\n' }}
+    {%- if messages[0]['role'] == 'system' %}
+        {{- messages[0]['content'] }}
+    {%- else %}
+        {{- 'You are Qwen, created by Alibaba Cloud. You are a helpful assistant.' }}
+    {%- endif %}
+    {{- "\n\n# Tools\n\nYou may call one or more functions to assist with the user query.\n\nYou are provided with function signatures within <tools></tools> XML tags:\n<tools>" }}
+    {%- for tool in tools %}
+        {{- "\n" }}
+        {{- tool | tojson }}
+    {%- endfor %}
+    {{- "\n</tools>\n\nFor each function call, return a json object with function name and arguments within <tool_call></tool_call> XML tags:\n<tool_call>\n{\"name\": <function-name>, \"arguments\": <args-json-object>}\n</tool_call><|im_end|>\n" }}
+{%- else %}
+    {%- if messages[0]['role'] == 'system' %}
+        {{- '<|im_start|>system\n' + messages[0]['content'] + '<|im_end|>\n' }}
+    {%- else %}
+        {{- '<|im_start|>system\nYou are Qwen, created by Alibaba Cloud. You are a helpful assistant.<|im_end|>\n' }}
+    {%- endif %}
+{%- endif %}
+{%- for message in messages %}
+    {%- if (message.role == "user") or (message.role == "system" and not loop.first) or (message.role == "assistant" and not message.tool_calls) %}
+        {{- '<|im_start|>' + message.role + '\n' + message.content + '<|im_end|>' + '\n' }}
+    {%- elif message.role == "assistant" %}
+        {{- '<|im_start|>' + message.role }}
+        {%- if message.content %}
+            {{- '\n' + message.content }}
+        {%- endif %}
+        {%- for tool_call in message.tool_calls %}
+            {%- if tool_call.function is defined %}
+                {%- set tool_call = tool_call.function %}
+            {%- endif %}
+            {{- '\n<tool_call>\n{"name": "' }}
+            {{- tool_call.name }}
+            {{- '", "arguments": ' }}
+            {{- tool_call.arguments | tojson }}
+            {{- '}\n</tool_call>' }}
+        {%- endfor %}
+        {{- '<|im_end|>\n' }}
+    {%- elif message.role == "tool" %}
+        {%- if (loop.index0 == 0) or (messages[loop.index0 - 1].role != "tool") %}
+            {{- '<|im_start|>user' }}
+        {%- endif %}
+        {{- '\n<tool_response>\n' }}
+        {{- message.content }}
+        {{- '\n</tool_response>' }}
+        {%- if loop.last or (messages[loop.index0 + 1].role != "tool") %}
+            {{- '<|im_end|>\n' }}
+        {%- endif %}
+    {%- endif %}
+{%- endfor %}
+{%- if add_generation_prompt %}
+    {{- '<|im_start|>assistant\n' }}
+{%- endif %}

documentation/v30b_delta_distillation_plan.md

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+# v30b delta-distillation plan
+
+Goal: make one standard PEFT LoRA adapter exceed v9 by focusing on verified delta wins.
+
+## Adapter
+
+```text
+adapter_v30b_delta_distilled_from_v9
+```
+
+## Difference from v30
+
+v30 used all v29 selector pass outputs conservatively and matched v9. v30b increases pressure on:
+
+```text
+v9 fails + v29 selector passes
+```
+
+These delta rows are repeated heavily, while keeping v9/clean/external retention.
+
+## Dataset mix
+
+Builder:
+
+```text
+scripts/build_v30b_delta_distill_dataset.py
+```
+
+Default repeats:
+
+```text
+delta wins:       80x
+all selector pass: 4x
+v9 pass retention: 6x
+clean verified:    2x
+external functional repair rows: 10x
+small synthetic:   1x
+```
+
+## Training
+
+Launcher:
+
+```text
+scripts/run_v30b_delta_distill.sh
+```
+
+Default:
+
+```text
+base adapter: adapter_v9_auto_distilled_direct
+epochs: 0.75
+lr: 7e-7
+max_length: 2048
+--drop-overlength
+```
+
+## Evaluation
+
+- VerilogEval direct
+- paper-style full
+- robust
+- alt
+
+## Caveat
+
+v30b is one adapter, but uses benchmark-targeted v29 selector outputs. It is a targeted/distilled experiment, not clean zero-shot VerilogEval evidence.

documentation/v30b_delta_distillation_results.md

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+# v30b delta-distilled single-adapter results
+
+v30b is the first post-v9 **single standard PEFT LoRA adapter** in this experiment series to improve direct VerilogEval pass count while preserving small external benchmark performance.
+
+```text
+adapter_v30b_delta_distilled_from_v9
+```
+
+## Motivation
+
+The v29 runtime selector reached 84/156 on VerilogEval by generating candidates from v9 plus multiple specialists and selecting with compile+simulation. That is a strong practical pipeline, but it is not a single deployable adapter.
+
+v30 attempted broad distillation of v29 into one adapter and matched v9 at 67/156. v30b instead focused training pressure on the delta:
+
+```text
+v9 fails + v29 selector passes
+```
+
+## Dataset
+
+Builder:
+
+```text
+scripts/build_v30b_delta_distill_dataset.py
+```
+
+Rows:
+
+```text
+total rows: 3358
+unique delta wins: 17
+unique selector pass rows: 84
+unique v9 pass retention rows: 67
+unique clean/manual verified rows: 382
+unique external functional rows: 18
+unique synthetic verified rows: 316
+```
+
+Repeat weights:
+
+```text
+delta wins:          80x
+all selector passes:  4x
+v9 pass retention:    6x
+clean verified:       2x
+external functional: 10x
+synthetic:            1x
+```
+
+The 17 delta-win problems were:
+
+```text
+Prob018_mux256to1
+Prob028_m2014_q4a
+Prob030_popcount255
+Prob042_vector4
+Prob045_edgedetect2
+Prob050_kmap1
+Prob054_edgedetect
+Prob056_ece241_2013_q7
+Prob060_m2014_q4k
+Prob063_review2015_shiftcount
+Prob075_counter_2bc
+Prob088_ece241_2014_q5b
+Prob097_mux9to1v
+Prob098_circuit7
+Prob121_2014_q3bfsm
+Prob130_circuit5
+Prob138_2012_q2fsm
+```
+
+Training used `--drop-overlength`; no rows were truncated.
+
+## Training
+
+Launcher:
+
+```text
+scripts/run_v30b_delta_distill.sh
+```
+
+Settings:
+
+```text
+base model: Qwen/Qwen2.5-Coder-7B-Instruct
+base adapter: adapter_v9_auto_distilled_direct
+output: adapter_v30b_delta_distilled_from_v9
+epochs: 0.75
+learning rate: 7e-7
+max length: 2048
+LoRA r: 16
+LoRA alpha: 32
+batch size: 1
+grad accum: 4
+warmup steps: 40
+```
+
+## Results
+
+### VerilogEval v2 direct
+
+| Adapter/system | Compile | Pass |
+|---|---:|---:|
+| v9 single adapter | — | 67/156 |
+| v29 multi-adapter selector | 150/156 | 84/156 |
+| v30 unified single adapter | 134/156 | 67/156 |
+| **v30b delta-distilled single adapter** | **141/156** | **71/156** |
+
+v30b improves single-adapter pass count by +4 over v9/v30.
+
+### External checks
+
+| Benchmark | Compile | Functional/task pass |
+|---|---:|---:|
+| Paper-style full | 30/30 | 26/30 task pass; 18/22 functional |
+| Robust | 14/15 | 6/10 functional |
+| Alt | 7/8 | 3/5 functional |
+
+These match the v9 baseline on the same external checks, so v30b did not show a regression on these small non-VerilogEval suites.
+
+## Interpretation
+
+v30b validates the paper-inspired lesson: simple broad SFT/distillation did not beat v9, but **verification-guided delta distillation** can transfer some of the v29 selector's gains into one standard adapter.
+
+Still, v30b remains far below the v29 verifier-selector pipeline because a single n=1 generation cannot reproduce multi-candidate search and runtime verification.
+
+## Caveat
+
+v30b is a single PEFT LoRA adapter, but it is trained with benchmark-targeted v29 selector outputs. Its VerilogEval result should be described as a targeted/distilled experiment, not a clean zero-shot leaderboard claim.
+
+## Published artifacts
+
+- Hugging Face adapter: `Pablo-Flores-Mollinedo/verilog-qwen2.5-coder-7b-v30b-delta-distilled-lora`
+- Main scripts:
+  - `scripts/build_v30b_delta_distill_dataset.py`
+  - `scripts/run_v30b_delta_distill.sh`
+- Result summary:
+  - `results/v30b_delta_distill/v30b_summary.json`
+  - `results/v30b_delta_distill/verilogeval_direct_summary.json`
+  - `results/v30b_delta_distill/verilogeval_direct_summary_results.jsonl`

results/dataset_summary.json

@@ -0,0 +1,91 @@
+{
+  "output": "data/v30b_delta_distill/v30b_delta_distill_train.jsonl",
+  "rows": 3358,
+  "unique_delta_wins": 17,
+  "unique_selector_pass": 84,
+  "unique_v9_pass": 67,
+  "unique_clean": 382,
+  "unique_external_functional": 18,
+  "unique_synthetic": 316,
+  "repeats": {
+    "delta_repeat": 80,
+    "selector_repeat": 4,
+    "v9_repeat": 6,
+    "clean_repeat": 2,
+    "external_repeat": 10,
+    "synthetic_repeat": 1
+  },
+  "by_category_unique": {
+    "delta": {
+      "comb_vector": 3,
+      "other": 1,
+      "counter_timer": 3,
+      "arith_datapath": 1,
+      "seq_shift": 5,
+      "case_kmap": 1,
+      "fsm_protocol": 3
+    },
+    "selector": {
+      "other": 6,
+      "comb_vector": 33,
+      "arith_datapath": 12,
+      "counter_timer": 11,
+      "seq_shift": 10,
+      "case_kmap": 2,
+      "fsm_protocol": 10
+    },
+    "v9": {
+      "comb_vector": 35,
+      "arith_datapath": 11,
+      "counter_timer": 9,
+      "seq_shift": 4,
+      "case_kmap": 1,
+      "fsm_protocol": 7
+    },
+    "clean": {
+      "comb_vector": 97,
+      "arith_datapath": 42,
+      "counter_timer": 91,
+      "seq_shift": 49,
+      "case_kmap": 19,
+      "fsm_protocol": 80,
+      "other": 4
+    },
+    "external": {
+      "arith_datapath": 5,
+      "comb_vector": 3,
+      "case_kmap": 3,
+      "seq_shift": 5,
+      "other": 1,
+      "counter_timer": 1
+    },
+    "synthetic": {
+      "counter_timer": 60,
+      "seq_shift": 60,
+      "fsm_protocol": 60,
+      "comb_vector": 60,
+      "arith_datapath": 16,
+      "case_kmap": 60
+    }
+  },
+  "delta_problems": [
+    "Prob018_mux256to1",
+    "Prob028_m2014_q4a",
+    "Prob030_popcount255",
+    "Prob042_vector4",
+    "Prob045_edgedetect2",
+    "Prob050_kmap1",
+    "Prob054_edgedetect",
+    "Prob056_ece241_2013_q7",
+    "Prob060_m2014_q4k",
+    "Prob063_review2015_shiftcount",
+    "Prob075_counter_2bc",
+    "Prob088_ece241_2014_q5b",
+    "Prob097_mux9to1v",
+    "Prob098_circuit7",
+    "Prob121_2014_q3bfsm",
+    "Prob130_circuit5",
+    "Prob138_2012_q2fsm"
+  ],
+  "caveat": "Single-adapter delta distillation from benchmark-targeted v29 selector wins; not clean zero-shot VerilogEval evidence."
+}

results/v30b_summary.json

@@ -0,0 +1,187 @@
+{
+  "adapter": "adapter_v30b_delta_distilled_from_v9",
+  "hf_repo": "Pablo-Flores-Mollinedo/verilog-qwen2.5-coder-7b-v30b-delta-distilled-lora",
+  "verilogeval_direct": {
+    "total": 156,
+    "compile": 141,
+    "passed": 71,
+    "compile_pct": 90.38461538461539,
+    "pass_pct": 45.51282051282051
+  },
+  "paper_full": {
+    "model": "v30b_delta_paper_full",
+    "adapter": "adapter_v30b_delta_distilled_from_v9",
+    "suite": "full",
+    "tasks": 30,
+    "k": 1,
+    "compile_any_pass": 30,
+    "compile_any_pct": 100.0,
+    "task_pass": 26,
+    "task_pass_pct": 86.66666666666667,
+    "functional_total": 22,
+    "functional_pass": 18,
+    "functional_pct": 81.81818181818181,
+    "by_category": {
+      "basic_comb": {
+        "total": 7,
+        "pass": 7,
+        "compile": 7,
+        "pass_pct": 100.0,
+        "compile_pct": 100.0
+      },
+      "arith": {
+        "total": 3,
+        "pass": 3,
+        "compile": 3,
+        "pass_pct": 100.0,
+        "compile_pct": 100.0
+      },
+      "bit_manip": {
+        "total": 4,
+        "pass": 4,
+        "compile": 4,
+        "pass_pct": 100.0,
+        "compile_pct": 100.0
+      },
+      "sequential": {
+        "total": 5,
+        "pass": 2,
+        "compile": 5,
+        "pass_pct": 40.0,
+        "compile_pct": 100.0
+      },
+      "fsm": {
+        "total": 3,
+        "pass": 2,
+        "compile": 3,
+        "pass_pct": 66.66666666666667,
+        "compile_pct": 100.0
+      },
+      "memory": {
+        "total": 3,
+        "pass": 3,
+        "compile": 3,
+        "pass_pct": 100.0,
+        "compile_pct": 100.0
+      },
+      "compile_rtl": {
+        "total": 5,
+        "pass": 5,
+        "compile": 5,
+        "pass_pct": 100.0,
+        "compile_pct": 100.0
+      }
+    }
+  },
+  "robust": {
+    "name": "v30b_delta_robust",
+    "suite": "robust",
+    "total": 15,
+    "compile_pass": 14,
+    "compile_pct": 93.33333333333333,
+    "functional_total": 10,
+    "functional_pass": 6,
+    "functional_pct": 60.0
+  },
+  "alt": {
+    "name": "v30b_delta_alt",
+    "suite": "alt",
+    "total": 8,
+    "compile_pass": 7,
+    "compile_pct": 87.5,
+    "functional_total": 5,
+    "functional_pass": 3,
+    "functional_pct": 60.0
+  },
+  "dataset": {
+    "output": "data/v30b_delta_distill/v30b_delta_distill_train.jsonl",
+    "rows": 3358,
+    "unique_delta_wins": 17,
+    "unique_selector_pass": 84,
+    "unique_v9_pass": 67,
+    "unique_clean": 382,
+    "unique_external_functional": 18,
+    "unique_synthetic": 316,
+    "repeats": {
+      "delta_repeat": 80,
+      "selector_repeat": 4,
+      "v9_repeat": 6,
+      "clean_repeat": 2,
+      "external_repeat": 10,
+      "synthetic_repeat": 1
+    },
+    "by_category_unique": {
+      "delta": {
+        "comb_vector": 3,
+        "other": 1,
+        "counter_timer": 3,
+        "arith_datapath": 1,
+        "seq_shift": 5,
+        "case_kmap": 1,
+        "fsm_protocol": 3
+      },
+      "selector": {
+        "other": 6,
+        "comb_vector": 33,
+        "arith_datapath": 12,
+        "counter_timer": 11,
+        "seq_shift": 10,
+        "case_kmap": 2,
+        "fsm_protocol": 10
+      },
+      "v9": {
+        "comb_vector": 35,
+        "arith_datapath": 11,
+        "counter_timer": 9,
+        "seq_shift": 4,
+        "case_kmap": 1,
+        "fsm_protocol": 7
+      },
+      "clean": {
+        "comb_vector": 97,
+        "arith_datapath": 42,
+        "counter_timer": 91,
+        "seq_shift": 49,
+        "case_kmap": 19,
+        "fsm_protocol": 80,
+        "other": 4
+      },
+      "external": {
+        "arith_datapath": 5,
+        "comb_vector": 3,
+        "case_kmap": 3,
+        "seq_shift": 5,
+        "other": 1,
+        "counter_timer": 1
+      },
+      "synthetic": {
+        "counter_timer": 60,
+        "seq_shift": 60,
+        "fsm_protocol": 60,
+        "comb_vector": 60,
+        "arith_datapath": 16,
+        "case_kmap": 60
+      }
+    },
+    "delta_problems": [
+      "Prob018_mux256to1",
+      "Prob028_m2014_q4a",
+      "Prob030_popcount255",
+      "Prob042_vector4",
+      "Prob045_edgedetect2",
+      "Prob050_kmap1",
+      "Prob054_edgedetect",
+      "Prob056_ece241_2013_q7",
+      "Prob060_m2014_q4k",
+      "Prob063_review2015_shiftcount",
+      "Prob075_counter_2bc",
+      "Prob088_ece241_2014_q5b",
+      "Prob097_mux9to1v",
+      "Prob098_circuit7",
+      "Prob121_2014_q3bfsm",
+      "Prob130_circuit5",
+      "Prob138_2012_q2fsm"
+    ],
+    "caveat": "Single-adapter delta distillation from benchmark-targeted v29 selector wins; not clean zero-shot VerilogEval evidence."
+  }
+}

results/verilogeval_direct_summary.json

@@ -0,0 +1,7 @@
+{
+  "total": 156,
+  "compile": 141,
+  "passed": 71,
+  "compile_pct": 90.38461538461539,
+  "pass_pct": 45.51282051282051
+}

results/verilogeval_direct_summary_results.jsonl

@@ -0,0 +1,156 @@
+{"problem": "Prob001_zero", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'zero' has no mismatches.\nHint: Total mismatched samples is 0 out of 20 samples\n\nSimulation finished at 102 ps\nMismatches: 0 in 20 samples\n"}
+{"problem": "Prob002_m2014_q4i", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 0 in 100 samples\n"}
+{"problem": "Prob003_step_one", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'one' has no mismatches.\nHint: Total mismatched samples is 0 out of 20 samples\n\nSimulation finished at 102 ps\nMismatches: 0 in 20 samples\n"}
+{"problem": "Prob004_vector2", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 110 samples\n\nSimulation finished at 550 ps\nMismatches: 0 in 110 samples\n"}
+{"problem": "Prob005_notgate", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 239 samples\n\nSimulation finished at 1196 ps\nMismatches: 0 in 239 samples\n"}
+{"problem": "Prob006_vectorr", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 218 samples\n\nSimulation finished at 1090 ps\nMismatches: 0 in 218 samples\n"}
+{"problem": "Prob007_wire", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 120 samples\n\nSimulation finished at 601 ps\nMismatches: 0 in 120 samples\n"}
+{"problem": "Prob008_m2014_q4h", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 0 in 100 samples\n"}
+{"problem": "Prob009_popcount3", "compile": false, "passed": false, "log": "dut.sv:12: warning: Numeric constant truncated to 3 bits.\ndut.sv:13: warning: Numeric constant truncated to 3 bits.\ndut.sv:14: syntax error\ndut.sv:14: error: Incomprehensible case expression.\ndut.sv:15: syntax error\ndut.sv:15: error: Incomprehensible case expression.\ndut.sv:16: syntax error\ndut.sv:16: error: Incomprehensible case expression.\ndut.sv:17: syntax error\ndut.sv:17: error: Incomprehensible case expression.\ndut.sv:18: syntax error\ndut.sv:18: error: Incomprehensible case expression.\ndut.sv:19: syntax error\ndut.sv:19: warning: Numeric constant truncated to 2 bits.\ndut.sv:19: error: Incomprehensible case expression.\n"}
+{"problem": "Prob010_mt2015_q4a", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has no mismatches.\nHint: Total mismatched samples is 0 out of 202 samples\n\nSimulation finished at 1011 ps\nMismatches: 0 in 202 samples\n"}
+{"problem": "Prob011_norgate", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 219 samples\n\nSimulation finished at 1096 ps\nMismatches: 0 in 219 samples\n"}
+{"problem": "Prob012_xnorgate", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 219 samples\n\nSimulation finished at 1096 ps\nMismatches: 0 in 219 samples\n"}
+{"problem": "Prob013_m2014_q4e", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 0 in 100 samples\n"}
+{"problem": "Prob014_andgate", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 219 samples\n\nSimulation finished at 1096 ps\nMismatches: 0 in 219 samples\n"}
+{"problem": "Prob015_vector1", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_hi' has no mismatches.\nHint: Output 'out_lo' has no mismatches.\nHint: Total mismatched samples is 0 out of 218 samples\n\nSimulation finished at 1090 ps\nMismatches: 0 in 218 samples\n"}
+{"problem": "Prob016_m2014_q4j", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'sum' has no mismatches.\nHint: Total mismatched samples is 0 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 0 in 100 samples\n"}
+{"problem": "Prob017_mux2to1v", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 114 samples\n\nSimulation finished at 570 ps\nMismatches: 0 in 114 samples\n"}
+{"problem": "Prob018_mux256to1", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 2000 samples\n\nSimulation finished at 10000 ps\nMismatches: 0 in 2000 samples\n"}
+{"problem": "Prob019_m2014_q4f", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 27 mismatches. First mismatch occurred at time 45.\nHint: Total mismatched samples is 27 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 27 in 100 samples\n"}
+{"problem": "Prob020_mt2015_eq2", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has no mismatches.\nHint: Total mismatched samples is 0 out of 2000 samples\n\nSimulation finished at 10001 ps\nMismatches: 0 in 2000 samples\n"}
+{"problem": "Prob021_mux256to1v", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 1943 mismatches. First mismatch occurred at time 10.\nHint: Total mismatched samples is 1943 out of 2000 samples\n\nSimulation finished at 10000 ps\nMismatches: 1943 in 2000 samples\n"}
+{"problem": "Prob022_mux2to1", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 122 samples\n\nSimulation finished at 610 ps\nMismatches: 0 in 122 samples\n"}
+{"problem": "Prob023_vector100r", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 200 samples\n\nSimulation finished at 1000 ps\nMismatches: 0 in 200 samples\n"}
+{"problem": "Prob024_hadd", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'sum' has no mismatches.\nHint: Output 'cout' has no mismatches.\nHint: Total mismatched samples is 0 out of 200 samples\n\nSimulation finished at 1000 ps\nMismatches: 0 in 200 samples\n"}
+{"problem": "Prob025_reduction", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'parity' has no mismatches.\nHint: Total mismatched samples is 0 out of 100 samples\n\nSimulation finished at 500 ps\nMismatches: 0 in 100 samples\n"}
+{"problem": "Prob026_alwaysblock1", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_assign' has no mismatches.\nHint: Output 'out_alwaysblock' has no mismatches.\nHint: Total mismatched samples is 0 out of 219 samples\n\nSimulation finished at 1096 ps\nMismatches: 0 in 219 samples\n"}
+{"problem": "Prob027_fadd", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'cout' has no mismatches.\nHint: Output 'sum' has no mismatches.\nHint: Total mismatched samples is 0 out of 214 samples\n\nSimulation finished at 1070 ps\nMismatches: 0 in 214 samples\n"}
+{"problem": "Prob028_m2014_q4a", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 0 in 100 samples\n"}
+{"problem": "Prob029_m2014_q4g", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 51 mismatches. First mismatch occurred at time 25.\nHint: Total mismatched samples is 51 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 51 in 100 samples\n"}
+{"problem": "Prob030_popcount255", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 215 samples\n\nSimulation finished at 1076 ps\nMismatches: 0 in 215 samples\n"}
+{"problem": "Prob031_dff", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 118 mismatches. First mismatch occurred at time 20.\nHint: Total mismatched samples is 118 out of 121 samples\n\nSimulation finished at 605 ps\nMismatches: 118 in 121 samples\n"}
+{"problem": "Prob032_vector0", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'outv' has no mismatches.\nHint: Output 'o2' has no mismatches.\nHint: Output 'o1' has no mismatches.\nHint: Output 'o0' has no mismatches.\nHint: Total mismatched samples is 0 out of 21 samples\n\nSimulation finished at 107 ps\nMismatches: 0 in 21 samples\n"}
+{"problem": "Prob033_ece241_2014_q1c", "compile": false, "passed": false, "log": "dut.sv:5: error: overflow is not a valid l-value in tb.top_module1.\ndut.sv:1:      : overflow is declared here as wire.\n1 error(s) during elaboration.\n"}
+{"problem": "Prob034_dff8", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 1 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 1 out of 41 samples\n\nSimulation finished at 206 ps\nMismatches: 1 in 41 samples\n"}
+{"problem": "Prob035_count1to10", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 439 samples\n\nSimulation finished at 2196 ps\nMismatches: 0 in 439 samples\n"}
+{"problem": "Prob036_ringer", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'ringer' has no mismatches.\nHint: Output 'motor' has no mismatches.\nHint: Total mismatched samples is 0 out of 19 samples\n\nSimulation finished at 97 ps\nMismatches: 0 in 19 samples\n"}
+{"problem": "Prob037_review2015_count1k", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 8027 samples\n\nSimulation finished at 40136 ps\nMismatches: 0 in 8027 samples\n"}
+{"problem": "Prob038_count15", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 421 samples\n\nSimulation finished at 2106 ps\nMismatches: 0 in 421 samples\n"}
+{"problem": "Prob039_always_if", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_assign' has no mismatches.\nHint: Output 'out_always' has no mismatches.\nHint: Total mismatched samples is 0 out of 114 samples\n\nSimulation finished at 570 ps\nMismatches: 0 in 114 samples\n"}
+{"problem": "Prob040_count10", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 439 samples\n\nSimulation finished at 2196 ps\nMismatches: 0 in 439 samples\n"}
+{"problem": "Prob041_dff8r", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 432 samples\n\nSimulation finished at 2161 ps\nMismatches: 0 in 432 samples\n"}
+{"problem": "Prob042_vector4", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 100 samples\n\nSimulation finished at 500 ps\nMismatches: 0 in 100 samples\n"}
+{"problem": "Prob043_vector5", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 100 samples\n\nSimulation finished at 500 ps\nMismatches: 0 in 100 samples\n"}
+{"problem": "Prob044_vectorgates", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_or_bitwise' has no mismatches.\nHint: Output 'out_or_logical' has no mismatches.\nHint: Output 'out_not' has no mismatches.\nHint: Total mismatched samples is 0 out of 261 samples\n\nSimulation finished at 1306 ps\nMismatches: 0 in 261 samples\n"}
+{"problem": "Prob045_edgedetect2", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'anyedge' has 146 mismatches. First mismatch occurred at time 170.\nHint: Total mismatched samples is 146 out of 228 samples\n\nSimulation finished at 1140 ps\nMismatches: 146 in 228 samples\n"}
+{"problem": "Prob046_dff8p", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 408 mismatches. First mismatch occurred at time 45.\nHint: Total mismatched samples is 408 out of 436 samples\n\nSimulation finished at 2181 ps\nMismatches: 408 in 436 samples\n"}
+{"problem": "Prob047_dff8ar", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Your reset should be asynchronous, but doesn't appear to be.\nHint: Output 'q' has 44 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 44 out of 436 samples\n\nSimulation finished at 2181 ps\nMismatches: 44 in 436 samples\n"}
+{"problem": "Prob048_m2014_q4c", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 0 in 100 samples\n"}
+{"problem": "Prob049_m2014_q4b", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 17 mismatches. First mismatch occurred at time 15.\nHint: Total mismatched samples is 17 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 17 in 100 samples\n"}
+{"problem": "Prob050_kmap1", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 90 mismatches. First mismatch occurred at time 30.\nHint: Total mismatched samples is 90 out of 219 samples\n\nSimulation finished at 1096 ps\nMismatches: 90 in 219 samples\n"}
+{"problem": "Prob051_gates4", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_and' has no mismatches.\nHint: Output 'out_or' has no mismatches.\nHint: Output 'out_xor' has no mismatches.\nHint: Total mismatched samples is 0 out of 234 samples\n\nSimulation finished at 1170 ps\nMismatches: 0 in 234 samples\n"}
+{"problem": "Prob052_gates100", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_and' has no mismatches.\nHint: Output 'out_or' has no mismatches.\nHint: Output 'out_xor' has no mismatches.\nHint: Total mismatched samples is 0 out of 433 samples\n\nSimulation finished at 2166 ps\nMismatches: 0 in 433 samples\n"}
+{"problem": "Prob053_m2014_q4d", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 1 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 1 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 1 in 100 samples\n"}
+{"problem": "Prob054_edgedetect", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'pedge' has no mismatches.\nHint: Total mismatched samples is 0 out of 227 samples\n\nSimulation finished at 1135 ps\nMismatches: 0 in 227 samples\n"}
+{"problem": "Prob055_conditional", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'min' has no mismatches.\nHint: Total mismatched samples is 0 out of 112 samples\n\nSimulation finished at 560 ps\nMismatches: 0 in 112 samples\n"}
+{"problem": "Prob056_ece241_2013_q7", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'Q' has no mismatches.\nHint: Total mismatched samples is 0 out of 422 samples\n\nSimulation finished at 2110 ps\nMismatches: 0 in 422 samples\n"}
+{"problem": "Prob057_kmap2", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 123 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 123 out of 232 samples\n\nSimulation finished at 1161 ps\nMismatches: 123 in 232 samples\n"}
+{"problem": "Prob058_alwaysblock2", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_assign' has no mismatches.\nHint: Output 'out_always_comb' has no mismatches.\nHint: Output 'out_always_ff' has no mismatches.\nHint: Total mismatched samples is 0 out of 219 samples\n\nSimulation finished at 1096 ps\nMismatches: 0 in 219 samples\n"}
+{"problem": "Prob059_wire4", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'w' has no mismatches.\nHint: Output 'x' has no mismatches.\nHint: Output 'y' has no mismatches.\nHint: Output 'z' has no mismatches.\nHint: Total mismatched samples is 0 out of 218 samples\n\nSimulation finished at 1090 ps\nMismatches: 0 in 218 samples\n"}
+{"problem": "Prob060_m2014_q4k", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 299 samples\n\nSimulation finished at 1496 ps\nMismatches: 0 in 299 samples\n"}
+{"problem": "Prob061_2014_q4a", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'Q' has no mismatches.\nHint: Total mismatched samples is 0 out of 200 samples\n\nSimulation finished at 1001 ps\nMismatches: 0 in 200 samples\n"}
+{"problem": "Prob062_bugs_mux2", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 110 mismatches. First mismatch occurred at time 20.\nHint: Total mismatched samples is 110 out of 114 samples\n\nSimulation finished at 570 ps\nMismatches: 110 in 114 samples\n"}
+{"problem": "Prob063_review2015_shiftcount", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 2071 samples\n\nSimulation finished at 10356 ps\nMismatches: 0 in 2071 samples\n"}
+{"problem": "Prob064_vector3", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'w' has 100 mismatches. First mismatch occurred at time 130.\nHint: Output 'x' has 101 mismatches. First mismatch occurred at time 130.\nHint: Output 'y' has 115 mismatches. First mismatch occurred at time 60.\nHint: Output 'z' has 126 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 126 out of 126 samples\n\nSimulation finished at 630 ps\nMismatches: 126 in 126 samples\n"}
+{"problem": "Prob065_7420", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'p1y' has no mismatches.\nHint: Output 'p2y' has no mismatches.\nHint: Total mismatched samples is 0 out of 239 samples\n\nSimulation finished at 1196 ps\nMismatches: 0 in 239 samples\n"}
+{"problem": "Prob066_edgecapture", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 225 mismatches. First mismatch occurred at time 100.\nHint: Total mismatched samples is 225 out of 266 samples\n\nSimulation finished at 1330 ps\nMismatches: 225 in 266 samples\n"}
+{"problem": "Prob067_countslow", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 499 samples\n\nSimulation finished at 2496 ps\nMismatches: 0 in 499 samples\n"}
+{"problem": "Prob068_countbcd", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'ena' has 39634 mismatches. First mismatch occurred at time 160.\nHint: Output 'q' has 39756 mismatches. First mismatch occurred at time 30.\nHint: Total mismatched samples is 39774 out of 39805 samples\n\nSimulation finished at 199026 ps\nMismatches: 39774 in 39805 samples\n"}
+{"problem": "Prob069_truthtable1", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'f' has 50 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 50 out of 58 samples\n\nSimulation finished at 290 ps\nMismatches: 50 in 58 samples\n"}
+{"problem": "Prob070_ece241_2013_q2", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_sop' has 36 mismatches. First mismatch occurred at time 20.\nHint: Output 'out_pos' has 27 mismatches. First mismatch occurred at time 30.\nHint: Total mismatched samples is 44 out of 107 samples\n\nSimulation finished at 535 ps\nMismatches: 44 in 107 samples\n"}
+{"problem": "Prob071_always_casez", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'pos' has 1 mismatches. First mismatch occurred at time 1415.\nHint: Total mismatched samples is 1 out of 346 samples\n\nSimulation finished at 1730 ps\nMismatches: 1 in 346 samples\n"}
+{"problem": "Prob072_thermostat", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'heater' has no mismatches.\nHint: Output 'aircon' has no mismatches.\nHint: Output 'fan' has no mismatches.\nHint: Total mismatched samples is 0 out of 248 samples\n\nSimulation finished at 1241 ps\nMismatches: 0 in 248 samples\n"}
+{"problem": "Prob073_dff16e", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 443 samples\n\nSimulation finished at 2216 ps\nMismatches: 0 in 443 samples\n"}
+{"problem": "Prob074_ece241_2014_q4", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has 45 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 45 out of 118 samples\n\nSimulation finished at 590 ps\nMismatches: 45 in 118 samples\n"}
+{"problem": "Prob075_counter_2bc", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'state' has no mismatches.\nHint: Total mismatched samples is 0 out of 1051 samples\n\nSimulation finished at 5256 ps\nMismatches: 0 in 1051 samples\n"}
+{"problem": "Prob076_always_case", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 118 samples\n\nSimulation finished at 590 ps\nMismatches: 0 in 118 samples\n"}
+{"problem": "Prob077_wire_decl", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Output 'out_n' has no mismatches.\nHint: Total mismatched samples is 0 out of 122 samples\n\nSimulation finished at 611 ps\nMismatches: 0 in 122 samples\n"}
+{"problem": "Prob078_dualedge", "compile": false, "passed": false, "log": "dut.sv:2: syntax error\ndut.sv:2: Syntax in assignment statement l-value.\n"}
+{"problem": "Prob079_fsm3onehot", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'next_state' has 141 mismatches. First mismatch occurred at time 10.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 141 out of 200 samples\n\nSimulation finished at 1001 ps\nMismatches: 141 in 200 samples\n"}
+{"problem": "Prob080_timer", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'tc' has no mismatches.\nHint: Total mismatched samples is 0 out of 7127 samples\n\nSimulation finished at 35636 ps\nMismatches: 0 in 7127 samples\n"}
+{"problem": "Prob081_7458", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'p1y' has no mismatches.\nHint: Output 'p2y' has no mismatches.\nHint: Total mismatched samples is 0 out of 439 samples\n\nSimulation finished at 2196 ps\nMismatches: 0 in 439 samples\n"}
+{"problem": "Prob082_lfsr32", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nTIMEOUT\nHint: Output 'q' has 199953 mismatches. First mismatch occurred at time 190.\nHint: Total mismatched samples is 199953 out of 200000 samples\n\nSimulation finished at 1000000 ps\nMismatches: 199953 in 200000 samples\n"}
+{"problem": "Prob083_mt2015_q4b", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has no mismatches.\nHint: Total mismatched samples is 0 out of 110 samples\n\nSimulation finished at 551 ps\nMismatches: 0 in 110 samples\n"}
+{"problem": "Prob084_ece241_2013_q12", "compile": false, "passed": false, "log": "dut.sv:9: syntax error\ndut.sv:6: error: syntax error in continuous assignment\n"}
+{"problem": "Prob085_shift4", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Your reset should be asynchronous, but doesn't appear to be.\nHint: Output 'q' has 73 mismatches. First mismatch occurred at time 40.\nHint: Total mismatched samples is 73 out of 427 samples\n\nSimulation finished at 2136 ps\nMismatches: 73 in 427 samples\n"}
+{"problem": "Prob086_lfsr5", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 4266 mismatches. First mismatch occurred at time 40.\nHint: Total mismatched samples is 4266 out of 4443 samples\n\nSimulation finished at 22216 ps\nMismatches: 4266 in 4443 samples\n"}
+{"problem": "Prob087_gates", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_and' has no mismatches.\nHint: Output 'out_or' has no mismatches.\nHint: Output 'out_xor' has no mismatches.\nHint: Output 'out_nand' has no mismatches.\nHint: Output 'out_nor' has no mismatches.\nHint: Output 'out_xnor' has no mismatches.\nHint: Output 'out_anotb' has no mismatches.\nHint: Total mismatched samples is 0 out of 210 samples\n\nSimulation finished at 1050 ps\nMismatches: 0 in 210 samples\n"}
+{"problem": "Prob088_ece241_2014_q5b", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Your reset doesn't seem to be working.\nHint: Output 'z' has 436 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 436 out of 436 samples\n\nSimulation finished at 2180 ps\nMismatches: 436 in 436 samples\n"}
+{"problem": "Prob089_ece241_2014_q5a", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has 393 mismatches. First mismatch occurred at time 20.\nHint: Total mismatched samples is 393 out of 436 samples\n\nSimulation finished at 2180 ps\nMismatches: 393 in 436 samples\n"}
+{"problem": "Prob090_circuit1", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 120 samples\n\nSimulation finished at 600 ps\nMismatches: 0 in 120 samples\n"}
+{"problem": "Prob091_2012_q2b", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'Y1' has 238 mismatches. First mismatch occurred at time 15.\nHint: Output 'Y3' has 325 mismatches. First mismatch occurred at time 20.\nHint: Total mismatched samples is 443 out of 600 samples\n\nSimulation finished at 3001 ps\nMismatches: 443 in 600 samples\n"}
+{"problem": "Prob092_gatesv100", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_both' has no mismatches.\nHint: Output 'out_any' has 201 mismatches. First mismatch occurred at time 5.\nHint: Output 'out_different' has no mismatches.\nHint: Total mismatched samples is 201 out of 201 samples\n\nSimulation finished at 1006 ps\nMismatches: 201 in 201 samples\n"}
+{"problem": "Prob093_ece241_2014_q3", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'mux_in' has 60 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 60 out of 60 samples\n\nSimulation finished at 300 ps\nMismatches: 60 in 60 samples\n"}
+{"problem": "Prob094_gatesv", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_both' has 116 mismatches. First mismatch occurred at time 5.\nHint: Output 'out_any' has 109 mismatches. First mismatch occurred at time 5.\nHint: Output 'out_different' has 160 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 172 out of 213 samples\n\nSimulation finished at 1066 ps\nMismatches: 172 in 213 samples\n"}
+{"problem": "Prob095_review2015_fsmshift", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'shift_ena' has no mismatches.\nHint: Total mismatched samples is 0 out of 200 samples\n\nSimulation finished at 1001 ps\nMismatches: 0 in 200 samples\n"}
+{"problem": "Prob096_review2015_fsmseq", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'start_shifting' has 306 mismatches. First mismatch occurred at time 50.\nHint: Total mismatched samples is 306 out of 643 samples\n\nSimulation finished at 3216 ps\nMismatches: 306 in 643 samples\n"}
+{"problem": "Prob097_mux9to1v", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 220 samples\n\nSimulation finished at 1100 ps\nMismatches: 0 in 220 samples\n"}
+{"problem": "Prob098_circuit7", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 120 mismatches. First mismatch occurred at time 20.\nHint: Total mismatched samples is 120 out of 123 samples\n\nSimulation finished at 615 ps\nMismatches: 120 in 123 samples\n"}
+{"problem": "Prob099_m2014_q6c", "compile": false, "passed": false, "log": "test.sv:71: error: port ``Y2'' is not a port of good1.\ntest.sv:71: error: port ``Y4'' is not a port of good1.\ntest.sv:77: error: port ``Y2'' is not a port of top_module1.\ntest.sv:77: error: port ``Y4'' is not a port of top_module1.\n4 error(s) during elaboration.\n"}
+{"problem": "Prob100_fsm3comb", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'next_state' has 70 mismatches. First mismatch occurred at time 10.\nHint: Output 'out' has 14 mismatches. First mismatch occurred at time 40.\nHint: Total mismatched samples is 70 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 70 in 100 samples\n"}
+{"problem": "Prob101_circuit4", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 53 mismatches. First mismatch occurred at time 25.\nHint: Total mismatched samples is 53 out of 121 samples\n\nSimulation finished at 605 ps\nMismatches: 53 in 121 samples\n"}
+{"problem": "Prob102_circuit3", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 64 mismatches. First mismatch occurred at time 25.\nHint: Total mismatched samples is 64 out of 121 samples\n\nSimulation finished at 605 ps\nMismatches: 64 in 121 samples\n"}
+{"problem": "Prob103_circuit2", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 121 samples\n\nSimulation finished at 605 ps\nMismatches: 0 in 121 samples\n"}
+{"problem": "Prob104_mt2015_muxdff", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'Q' has 1 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 1 out of 199 samples\n\nSimulation finished at 996 ps\nMismatches: 1 in 199 samples\n"}
+{"problem": "Prob105_rotate100", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 3292 mismatches. First mismatch occurred at time 60.\nHint: Total mismatched samples is 3292 out of 4005 samples\n\nSimulation finished at 20026 ps\nMismatches: 3292 in 4005 samples\n"}
+{"problem": "Prob106_always_nolatches", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'left' has no mismatches.\nHint: Output 'down' has no mismatches.\nHint: Output 'right' has no mismatches.\nHint: Output 'up' has no mismatches.\nHint: Total mismatched samples is 0 out of 30020 samples\n\nSimulation finished at 150100 ps\nMismatches: 0 in 30020 samples\n"}
+{"problem": "Prob107_fsm1s", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 137 mismatches. First mismatch occurred at time 30.\nHint: Total mismatched samples is 137 out of 230 samples\n\nSimulation finished at 1151 ps\nMismatches: 137 in 230 samples\n"}
+{"problem": "Prob108_rule90", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 6022 mismatches. First mismatch occurred at time 50.\nHint: Total mismatched samples is 6022 out of 7121 samples\n\nSimulation finished at 35606 ps\nMismatches: 6022 in 7121 samples\n"}
+{"problem": "Prob109_fsm1", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 228 samples\n\nSimulation finished at 1141 ps\nMismatches: 0 in 228 samples\n"}
+{"problem": "Prob110_fsm2", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 241 samples\n\nSimulation finished at 1206 ps\nMismatches: 0 in 241 samples\n"}
+{"problem": "Prob111_fsm2s", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Total mismatched samples is 0 out of 241 samples\n\nSimulation finished at 1206 ps\nMismatches: 0 in 241 samples\n"}
+{"problem": "Prob112_always_case2", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'pos' has 61 mismatches. First mismatch occurred at time 90.\nHint: Total mismatched samples is 61 out of 94 samples\n\nSimulation finished at 470 ps\nMismatches: 61 in 94 samples\n"}
+{"problem": "Prob113_2012_q1g", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'f' has 30 mismatches. First mismatch occurred at time 10.\nHint: Total mismatched samples is 30 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 30 in 100 samples\n"}
+{"problem": "Prob114_bugs_case", "compile": false, "passed": false, "log": "dut.sv:4: syntax error\ndut.sv:5: error: Incomprehensible case expression.\ndut.sv:5: syntax error\ndut.sv:6: error: Incomprehensible case expression.\ndut.sv:6: syntax error\ndut.sv:7: error: Incomprehensible case expression.\ndut.sv:7: syntax error\ndut.sv:8: error: Incomprehensible case expression.\ndut.sv:8: syntax error\ndut.sv:9: error: Incomprehensible case expression.\ndut.sv:9: syntax error\ndut.sv:10: error: Incomprehensible case expression.\ndut.sv:10: syntax error\ndut.sv:11: error: Incomprehensible case expression.\ndut.sv:11: syntax error\ndut.sv:12: error: Incomprehensible case expression.\ndut.sv:12: syntax error\ndut.sv:13: error: Incomprehensible case expression.\ndut.sv:13: syntax error\ndut.sv:14: error: Incomprehensible case expression.\n"}
+{"problem": "Prob115_shift18", "compile": false, "passed": false, "log": "dut.sv:8: warning: extra digits given for sized binary constant.\ndut.sv:8: syntax error\ndut.sv:8: error: malformed statement\n"}
+{"problem": "Prob116_m2014_q3", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'f' has 40 mismatches. First mismatch occurred at time 10.\nHint: Total mismatched samples is 40 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 40 in 100 samples\n"}
+{"problem": "Prob117_circuit9", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 244 mismatches. First mismatch occurred at time 10.\nHint: Total mismatched samples is 244 out of 245 samples\n\nSimulation finished at 1225 ps\nMismatches: 244 in 245 samples\n"}
+{"problem": "Prob118_history_shift", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'predict_history' has 980 mismatches. First mismatch occurred at time 220.\nHint: Total mismatched samples is 980 out of 2055 samples\n\nSimulation finished at 10276 ps\nMismatches: 980 in 2055 samples\n"}
+{"problem": "Prob119_fsm3", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 56 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 56 out of 230 samples\n\nSimulation finished at 1151 ps\nMismatches: 56 in 230 samples\n"}
+{"problem": "Prob120_fsm3s", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 56 mismatches. First mismatch occurred at time 40.\nHint: Total mismatched samples is 56 out of 230 samples\n\nSimulation finished at 1151 ps\nMismatches: 56 in 230 samples\n"}
+{"problem": "Prob121_2014_q3bfsm", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has 516 mismatches. First mismatch occurred at time 30.\nHint: Total mismatched samples is 516 out of 1006 samples\n\nSimulation finished at 5031 ps\nMismatches: 516 in 1006 samples\n"}
+{"problem": "Prob122_kmap4", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 142 mismatches. First mismatch occurred at time 20.\nHint: Total mismatched samples is 142 out of 232 samples\n\nSimulation finished at 1161 ps\nMismatches: 142 in 232 samples\n"}
+{"problem": "Prob123_bugs_addsubz", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has no mismatches.\nHint: Output 'result_is_zero' has no mismatches.\nHint: Total mismatched samples is 0 out of 118 samples\n\nSimulation finished at 590 ps\nMismatches: 0 in 118 samples\n"}
+{"problem": "Prob124_rule110", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 6220 mismatches. First mismatch occurred at time 40.\nHint: Total mismatched samples is 6220 out of 6283 samples\n\nSimulation finished at 31416 ps\nMismatches: 6220 in 6283 samples\n"}
+{"problem": "Prob125_kmap3", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out' has 124 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 124 out of 232 samples\n\nSimulation finished at 1161 ps\nMismatches: 124 in 232 samples\n"}
+{"problem": "Prob126_circuit6", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has no mismatches.\nHint: Total mismatched samples is 0 out of 113 samples\n\nSimulation finished at 565 ps\nMismatches: 0 in 113 samples\n"}
+{"problem": "Prob127_lemmings1", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Your reset doesn't seem to be working.\nHint: Output 'walk_left' has 133 mismatches. First mismatch occurred at time 5.\nHint: Output 'walk_right' has 137 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 205 out of 229 samples\n\nSimulation finished at 1146 ps\nMismatches: 205 in 229 samples\n"}
+{"problem": "Prob128_fsm_ps2", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'done' has no mismatches.\nHint: Total mismatched samples is 0 out of 400 samples\n\nSimulation finished at 2001 ps\nMismatches: 0 in 400 samples\n"}
+{"problem": "Prob129_ece241_2013_q8", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has 287 mismatches. First mismatch occurred at time 5.\nHint: Total mismatched samples is 287 out of 440 samples\n\nSimulation finished at 2200 ps\nMismatches: 287 in 440 samples\n"}
+{"problem": "Prob130_circuit5", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 40 mismatches. First mismatch occurred at time 20.\nHint: Total mismatched samples is 40 out of 141 samples\n\nSimulation finished at 705 ps\nMismatches: 40 in 141 samples\n"}
+{"problem": "Prob131_mt2015_q4", "compile": false, "passed": false, "log": "test.sv:68: error: Unknown module type: TopModule\n2 error(s) during elaboration.\n*** These modules were missing:\n        TopModule referenced 1 times.\n***\n"}
+{"problem": "Prob132_always_if2", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'shut_off_computer' has no mismatches.\nHint: Output 'keep_driving' has 41 mismatches. First mismatch occurred at time 30.\nHint: Total mismatched samples is 41 out of 121 samples\n\nSimulation finished at 605 ps\nMismatches: 41 in 121 samples\n"}
+{"problem": "Prob133_2014_q3fsm", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has 174 mismatches. First mismatch occurred at time 80.\nHint: Total mismatched samples is 174 out of 1414 samples\n\nSimulation finished at 7071 ps\nMismatches: 174 in 1414 samples\n"}
+{"problem": "Prob134_2014_q3c", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'Y0' has 67 mismatches. First mismatch occurred at time 10.\nHint: Output 'z' has 22 mismatches. First mismatch occurred at time 10.\nHint: Total mismatched samples is 78 out of 200 samples\n\nSimulation finished at 1001 ps\nMismatches: 78 in 200 samples\n"}
+{"problem": "Prob135_m2014_q6b", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'Y1' has 27 mismatches. First mismatch occurred at time 20.\nHint: Total mismatched samples is 27 out of 100 samples\n\nSimulation finished at 501 ps\nMismatches: 27 in 100 samples\n"}
+{"problem": "Prob136_m2014_q6", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has 76 mismatches. First mismatch occurred at time 230.\nHint: Total mismatched samples is 76 out of 200 samples\n\nSimulation finished at 1001 ps\nMismatches: 76 in 200 samples\n"}
+{"problem": "Prob137_fsm_serial", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'done' has 166 mismatches. First mismatch occurred at time 10.\nHint: Total mismatched samples is 166 out of 905 samples\n\nSimulation finished at 4526 ps\nMismatches: 166 in 905 samples\n"}
+{"problem": "Prob138_2012_q2fsm", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'z' has 88 mismatches. First mismatch occurred at time 210.\nHint: Total mismatched samples is 88 out of 400 samples\n\nSimulation finished at 2001 ps\nMismatches: 88 in 400 samples\n"}
+{"problem": "Prob139_2013_q2bfsm", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'f' has 312 mismatches. First mismatch occurred at time 20.\nHint: Output 'g' has 514 mismatches. First mismatch occurred at time 60.\nHint: Total mismatched samples is 663 out of 1002 samples\n\nSimulation finished at 5011 ps\nMismatches: 663 in 1002 samples\n"}
+{"problem": "Prob140_fsm_hdlc", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'disc' has 98 mismatches. First mismatch occurred at time 70.\nHint: Output 'flag' has 82 mismatches. First mismatch occurred at time 80.\nHint: Output 'err' has 210 mismatches. First mismatch occurred at time 90.\nHint: Total mismatched samples is 328 out of 801 samples\n\nSimulation finished at 4006 ps\nMismatches: 328 in 801 samples\n"}
+{"problem": "Prob141_count_clock", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Your reset doesn't seem to be working.\nHint: Clock seems to reset to 00:x0:x0 AM (Should be 12:00:00 AM).\nTIMEOUT\nHint: Output 'pm' has 86400 mismatches. First mismatch occurred at time 434270.\nHint: Output 'hh' has 199999 mismatches. First mismatch occurred at time 10.\nHint: Output 'mm' has 199999 mismatches. First mismatch occurred at time 10.\nHint: Output 'ss' has 199999 mismatches. First mismatch occurred at time 10.\nHint: Total mismatched samples is 199999 out of 200000 samples\n\nSimulation finished at 1000000 ps\nMismatches: 199999 in 200000 samples\n"}
+{"problem": "Prob142_lemmings2", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Your reset doesn't seem to be working.\nHint: Output 'walk_left' has 235 mismatches. First mismatch occurred at time 5.\nHint: Output 'walk_right' has 165 mismatches. First mismatch occurred at time 110.\nHint: Output 'aaah' has 78 mismatches. First mismatch occurred at time 100.\nHint: Total mismatched samples is 441 out of 441 samples\n\nSimulation finished at 2206 ps\nMismatches: 441 in 441 samples\n"}
+{"problem": "Prob143_fsm_onehot", "compile": false, "passed": false, "log": "dut.sv:6: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:6: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\ndut.sv:10: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:10: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\ndut.sv:14: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:14: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\ndut.sv:18: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:18: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\ndut.sv:22: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:22: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\ndut.sv:26: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:26: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\ndut.sv:30: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:30: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\ndut.sv:34: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:34: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\ndut.sv:38: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:38: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\ndut.sv:42: error: out1 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out1 is declared here as wire.\ndut.sv:42: error: out2 is not a valid l-value in tb.top_module1.\ndut.sv:1:      : out2 is declared here as wire.\n20 error(s) during elaboration.\n"}
+{"problem": "Prob144_conwaylife", "compile": false, "passed": false, "log": "dut.sv:13: syntax error\ndut.sv:13: error: malformed statement\n"}
+{"problem": "Prob145_circuit8", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'p' has 112 mismatches. First mismatch occurred at time 90.\nHint: Output 'q' has 133 mismatches. First mismatch occurred at time 120.\nHint: Total mismatched samples is 173 out of 240 samples\n\nSimulation finished at 1200 ps\nMismatches: 173 in 240 samples\n"}
+{"problem": "Prob146_fsm_serialdata", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_byte' has 32 mismatches. First mismatch occurred at time 850.\nHint: Output 'done' has 200 mismatches. First mismatch occurred at time 320.\nHint: Total mismatched samples is 226 out of 905 samples\n\nSimulation finished at 4526 ps\nMismatches: 226 in 905 samples\n"}
+{"problem": "Prob147_circuit10", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'q' has 12 mismatches. First mismatch occurred at time 50.\nHint: Output 'state' has 6 mismatches. First mismatch occurred at time 60.\nHint: Total mismatched samples is 16 out of 232 samples\n\nSimulation finished at 1160 ps\nMismatches: 16 in 232 samples\n"}
+{"problem": "Prob148_2013_q2afsm", "compile": true, "passed": true, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'g' has no mismatches.\nHint: Total mismatched samples is 0 out of 1054 samples\n\nSimulation finished at 5271 ps\nMismatches: 0 in 1054 samples\n"}
+{"problem": "Prob149_ece241_2013_q4", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Your reset doesn't seem to be working.\nHint: Output 'fr2' has 860 mismatches. First mismatch occurred at time 90.\nHint: Output 'fr1' has 1462 mismatches. First mismatch occurred at time 30.\nHint: Output 'fr0' has 2031 mismatches. First mismatch occurred at time 30.\nHint: Output 'dfr' has 1240 mismatches. First mismatch occurred at time 10.\nHint: Total mismatched samples is 2039 out of 2040 samples\n\nSimulation finished at 10200 ps\nMismatches: 2039 in 2040 samples\n"}
+{"problem": "Prob150_review2015_fsmonehot", "compile": false, "passed": false, "log": "dut.sv:34: warning: Numeric constant truncated to 10 bits.\ndut.sv:37: warning: Numeric constant truncated to 10 bits.\ndut.sv:40: warning: Numeric constant truncated to 10 bits.\ndut.sv:43: warning: Numeric constant truncated to 10 bits.\ndut.sv:26: error: Could not find variable ``B0_next'' in ``tb.top_module1''\ndut.sv:29: error: shift_ena is not a valid l-value in tb.top_module1.\ndut.sv:1:      : shift_ena is declared here as wire.\ndut.sv:29: error: Could not find variable ``B1_next'' in ``tb.top_module1''\ndut.sv:32: error: shift_ena is not a valid l-value in tb.top_module1.\ndut.sv:1:      : shift_ena is declared here as wire.\ndut.sv:32: error: Could not find variable ``B2_next'' in ``tb.top_module1''\ndut.sv:35: error: shift_ena is not a valid l-value in tb.top_module1.\ndut.sv:1:      : shift_ena is declared here as wire.\ndut.sv:38: error: counting is not a valid l-value in tb.top_module1.\ndut.sv:1:      : counting is declared here as wire.\ndut.sv:41: error: counting is not a valid l-value in tb.top_module1.\ndut.sv:1:      : counting is declared here as wire.\ndut.sv:44: error: done is not a valid l-value in tb.top_module1.\ndut.sv:1:      : done is declared here as wire.\n9 error(s) during elaboration.\n"}
+{"problem": "Prob151_review2015_fsm", "compile": false, "passed": false, "log": "ref.sv:21: sorry: This cast operation is not yet supported.\nref.sv:22: sorry: This cast operation is not yet supported.\nref.sv:23: sorry: This cast operation is not yet supported.\nref.sv:24: sorry: This cast operation is not yet supported.\nref.sv:29: sorry: This cast operation is not yet supported.\nref.sv:30: sorry: This cast operation is not yet supported.\nref.sv:31: sorry: This cast operation is not yet supported.\n7 error(s) during elaboration.\n"}
+{"problem": "Prob152_lemmings3", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'walk_left' has 94 mismatches. First mismatch occurred at time 5.\nHint: Output 'walk_right' has 253 mismatches. First mismatch occurred at time 5.\nHint: Output 'aaah' has 65 mismatches. First mismatch occurred at time 150.\nHint: Output 'digging' has 203 mismatches. First mismatch occurred at time 120.\nHint: Total mismatched samples is 310 out of 443 samples\n\nSimulation finished at 2216 ps\nMismatches: 310 in 443 samples\n"}
+{"problem": "Prob153_gshare", "compile": false, "passed": false, "log": "dut.sv:6: syntax error\ndut.sv:6: error: malformed statement\n"}
+{"problem": "Prob154_fsm_ps2data", "compile": true, "passed": false, "log": "VCD info: dumpfile wave.vcd opened for output.\nHint: Output 'out_bytes' has 490 mismatches. First mismatch occurred at time 210.\nHint: Output 'done' has 730 mismatches. First mismatch occurred at time 210.\nHint: Total mismatched samples is 946 out of 1619 samples\n\nSimulation finished at 8096 ps\nMismatches: 946 in 1619 samples\n"}
+{"problem": "Prob155_lemmings4", "compile": false, "passed": false, "log": "dut.sv:31: warning: Numeric constant truncated to 4 bits.\ndut.sv:5: error: Unable to bind wire/reg/memory `state_change' in `tb.top_module1'\ndut.sv:5: error: Failed to evaluate event expression 'state_change'.\n2 error(s) during elaboration.\n"}
+{"problem": "Prob156_review2015_fancytimer", "compile": false, "passed": false, "log": "ref.sv:25: sorry: This cast operation is not yet supported.\nref.sv:26: sorry: This cast operation is not yet supported.\nref.sv:27: sorry: This cast operation is not yet supported.\nref.sv:28: sorry: This cast operation is not yet supported.\nref.sv:33: sorry: This cast operation is not yet supported.\nref.sv:34: sorry: This cast operation is not yet supported.\nref.sv:35: sorry: This cast operation is not yet supported.\n7 error(s) during elaboration.\n"}

scripts/build_v30b_delta_distill_dataset.py

@@ -0,0 +1,350 @@
+#!/usr/bin/env python3
+"""Build v30b delta-distillation dataset.
+
+Purpose: make a *single* adapter beat v9 by focusing training pressure on the
+small delta where v9 fails but v29 verifier-selector passes, while retaining
+v9/general Verilog behavior.
+
+Main signal:
+- delta_wins: v29 selector passed and v9 direct did not pass.
+
+Retention:
+- v9 passed outputs.
+- clean/manual verified non-reference rows.
+- hand-written paper/robust-style functional rows verified with iverilog.
+- small verified synthetic rows from v29 gate data.
+
+Caveat: delta rows are benchmark-targeted distilled outputs, not clean zero-shot
+leaderboard evidence.
+"""
+import argparse
+import hashlib
+import json
+import random
+import shutil
+import subprocess
+import sys
+import tempfile
+from pathlib import Path
+
+ROOT = Path(__file__).resolve().parents[1]
+if str(ROOT) not in sys.path:
+    sys.path.insert(0, str(ROOT))
+
+CLEAN_INPUTS = [
+    "teacher_solutions/formatted_benchmarks/clean_or_verified_non_reference_seeded.jsonl",
+    "teacher_solutions/formatted_benchmarks/manual_clean_verilogeval.jsonl",
+    "teacher_solutions/manual_clean_verilogeval_v1_codecomplete/solutions_all.jsonl",
+    "teacher_solutions/formatted_benchmarks/rtllm_ir_verified.jsonl",
+    "teacher_solutions/formatted_benchmarks/paper_style_internal.jsonl",
+    "data/v15_clean_multibench_teacher_direct.jsonl",
+]
+CATEGORIES = ["comb_vector", "counter_timer", "seq_shift", "case_kmap", "fsm_protocol", "arith_datapath", "other"]
+
+
+def read_jsonl(path):
+    path = Path(path)
+    if not path.exists():
+        return []
+    out = []
+    for line in path.read_text(errors="ignore").splitlines():
+        if line.strip():
+            try:
+                out.append(json.loads(line))
+            except json.JSONDecodeError:
+                pass
+    return out
+
+
+def digest(row):
+    return hashlib.sha256((row.get("spec", "") + "\n---\n" + row.get("code", "")).encode()).hexdigest()
+
+
+def classify(problem="", spec="", category="", code=""):
+    text = " ".join([problem or "", spec or "", category or "", code[:400] or ""]).lower()
+    if any(k in text for k in ["fsm", "state machine", "lemmings", "ps/2", "ps2", "serial", "hdlc", "protocol", "sequence detector", "traffic", "vending"]):
+        return "fsm_protocol"
+    if any(k in text for k in ["counter", "count", "timer", "clock", "bcd", "modulo", "period", "pulse", "pwm", "crc"]):
+        return "counter_timer"
+    if any(k in text for k in ["dff", "flip-flop", "flip flop", "edge", "shift", "rotate", "lfsr", "rule90", "rule110", "history", "gshare", "register"]):
+        return "seq_shift"
+    if any(k in text for k in ["kmap", "k-map", "truth", "minterm", "casez", "casex", "priority", "encoder", "decoder", "popcount", "leading_one"]):
+        return "case_kmap"
+    if any(k in text for k in ["adder", "add", "subtract", "sum", "carry", "overflow", "alu", "multiply", "divide", "signed", "saturat", "compare", "arithmetic", "abs_value"]):
+        return "arith_datapath"
+    if any(k in text for k in ["mux", "vector", "bitwise", "gate", "circuit", "wire", "reduction", "xor", "and", "or", "not", "ram", "regfile"]):
+        return "comb_vector"
+    return "other"
+
+
+def norm(row, source, role, max_chars, forced_cat=None):
+    spec = (row.get("spec") or row.get("prompt") or "").strip()
+    code = (row.get("code") or row.get("solution") or "").strip()
+    if not spec or not code or "module" not in code.lower() or "endmodule" not in code.lower():
+        return None
+    if row.get("used_reference_as_solution", False):
+        return None
+    if len(spec) + len(code) > max_chars:
+        return None
+    cat = forced_cat or row.get("v30_category") or row.get("v29_category") or classify(row.get("problem", ""), spec, row.get("category", ""), code)
+    return {
+        "spec": spec,
+        "code": code + "\n",
+        "problem": row.get("problem"),
+        "benchmark": row.get("benchmark", "unknown"),
+        "source": source,
+        "verified": bool(row.get("verified", True)),
+        "used_reference_as_solution": False,
+        "used_adapter": bool(row.get("used_adapter", False)),
+        "v30b_role": role,
+        "v30b_category": cat,
+    }
+
+
+def prompt_for(repo, problem):
+    for sub in ["dataset_spec-to-rtl", "dataset_code-complete-iccad2023"]:
+        p = Path(repo) / sub / f"{problem}_prompt.txt"
+        if p.exists():
+            return p.read_text(errors="ignore").strip()
+    return ""
+
+
+def collect_selected_outputs(repo, selector_build, v9_build, max_chars):
+    repo = Path(repo); selector_build = Path(selector_build); v9_build = Path(v9_build)
+    v9 = {r.get("problem"): r for r in read_jsonl(v9_build / "direct_summary_results.jsonl")}
+    selector_rows, delta_rows = [], []
+    for rec in read_jsonl(selector_build / "direct_summary_results.jsonl"):
+        if not rec.get("passed"):
+            continue
+        problem = rec.get("problem")
+        spec = prompt_for(repo, problem)
+        code_path = selector_build / problem / f"{problem}_sample01.sv"
+        if not spec or not code_path.exists():
+            continue
+        raw = {"spec": spec, "code": code_path.read_text(errors="ignore"), "problem": problem, "benchmark": "VerilogEval_v2", "verified": True, "used_adapter": True}
+        is_delta = not bool(v9.get(problem, {}).get("passed"))
+        role = "delta_v9_fail_v29_pass" if is_delta else "selector_pass_retention"
+        row = norm(raw, "v30b_v29_selector_pass", role, max_chars, forced_cat=rec.get("category"))
+        if row:
+            row["selected_adapter"] = rec.get("selected_adapter")
+            selector_rows.append(row)
+            if is_delta:
+                delta_rows.append(row)
+    return selector_rows, delta_rows
+
+
+def collect_v9_pass(repo, v9_build, max_chars):
+    repo = Path(repo); v9_build = Path(v9_build)
+    rows = []
+    for rec in read_jsonl(v9_build / "direct_summary_results.jsonl"):
+        if not rec.get("passed"):
+            continue
+        problem = rec.get("problem")
+        spec = prompt_for(repo, problem)
+        code_path = v9_build / problem / f"{problem}_sample01.sv"
+        if not spec or not code_path.exists():
+            continue
+        raw = {"spec": spec, "code": code_path.read_text(errors="ignore"), "problem": problem, "benchmark": "VerilogEval_v2", "verified": True, "used_adapter": True}
+        r = norm(raw, "v30b_v9_pass_retention", "v9_pass_retention", max_chars)
+        if r:
+            rows.append(r)
+    return rows
+
+
+def collect_clean(max_chars):
+    rows, seen = [], set()
+    for path in CLEAN_INPUTS:
+        for raw in read_jsonl(path):
+            r = norm(raw, f"v30b_clean:{path}", "clean_verified_retention", max_chars)
+            if not r or not r.get("verified", True):
+                continue
+            key = digest(r)
+            if key in seen:
+                continue
+            seen.add(key)
+            rows.append(r)
+    return rows
+
+
+def collect_synth(path, per_cat, seed, max_chars):
+    rng = random.Random(seed)
+    by = {c: [] for c in CATEGORIES}
+    seen = set()
+    for raw in read_jsonl(path):
+        src = str(raw.get("source", "")).lower()
+        bench = str(raw.get("benchmark", "")).lower()
+        if "synthetic" not in src and "synthetic" not in bench:
+            continue
+        if raw.get("verified") is False:
+            continue
+        r = norm(raw, "v30b_small_verified_synthetic", "small_verified_synthetic", max_chars)
+        if not r:
+            continue
+        key = digest(r)
+        if key in seen:
+            continue
+        seen.add(key)
+        by.setdefault(r["v30b_category"], []).append(r)
+    rows = []
+    for c, rs in by.items():
+        rng.shuffle(rs)
+        rows.extend(rs[:per_cat])
+    rng.shuffle(rows)
+    return rows
+
+
+def run_iverilog_ok(code, tb):
+    if not shutil.which("iverilog"):
+        return True
+    with tempfile.TemporaryDirectory() as td:
+        td = Path(td)
+        (td / "dut.v").write_text(code)
+        cmd = ["iverilog", "-g2012", "-o", str(td / "sim.out"), str(td / "dut.v")]
+        if tb:
+            (td / "tb.v").write_text(tb)
+            cmd.append(str(td / "tb.v"))
+        try:
+            c = subprocess.run(cmd, capture_output=True, text=True, timeout=20)
+            if c.returncode:
+                return False
+            if not tb:
+                return True
+            v = subprocess.run([str(td / "sim.out")], capture_output=True, text=True, timeout=20)
+            txt = v.stdout + v.stderr
+            return v.returncode == 0 and "PASS" in txt and "FAIL" not in txt
+        except subprocess.TimeoutExpired:
+            return False
+
+
+def paper_repair_rows(max_chars):
+    # Hand-written external rows for general RTL skills. Testbenches come from paper-style harness.
+    try:
+        from src.paper_style_verilog_benchmark import TASKS
+    except Exception:
+        TASKS = []
+    code = {
+        "comb_half_adder": "module half_adder(input a, input b, output sum, output carry); assign sum = a ^ b; assign carry = a & b; endmodule",
+        "comb_full_adder": "module full_adder(input a, input b, input cin, output sum, output cout); assign {cout,sum} = a + b + cin; endmodule",
+        "comb_mux4": "module mux4to1(input [7:0] a,b,c,d, input [1:0] sel, output reg [7:0] y); always @(*) begin case(sel) 2'd0:y=a; 2'd1:y=b; 2'd2:y=c; default:y=d; endcase end endmodule",
+        "comb_decoder": "module decoder_3to8(input [2:0] in, output [7:0] out); assign out = 8'b1 << in; endmodule",
+        "comb_priority": "module priority_encoder_8to3(input [7:0] in, output reg [2:0] out, output valid); assign valid = |in; always @(*) begin out=0; if(in[7]) out=7; else if(in[6]) out=6; else if(in[5]) out=5; else if(in[4]) out=4; else if(in[3]) out=3; else if(in[2]) out=2; else if(in[1]) out=1; else out=0; end endmodule",
+        "comb_comparator": "module comparator_8bit(input [7:0] a, input [7:0] b, output eq, output gt, output lt); assign eq=(a==b); assign gt=(a>b); assign lt=(a<b); endmodule",
+        "comb_parity_explicit": "module parity_generator(input [7:0] data, output even_parity, output odd_parity); assign even_parity = ^data; assign odd_parity = ~(^data); endmodule",
+        "arith_alu4": "module alu_4bit(input [3:0] a, input [3:0] b, input [2:0] op, output reg [3:0] y, output zero); always @(*) begin case(op) 3'd0:y=a+b; 3'd1:y=a-b; 3'd2:y=a&b; 3'd3:y=a|b; 3'd4:y=a^b; default:y=0; endcase end assign zero=(y==0); endmodule",
+        "arith_satadd": "module sat_adder8(input signed [7:0] a, input signed [7:0] b, output reg signed [7:0] sum); reg signed [8:0] tmp; always @(*) begin tmp = a + b; if(tmp > 9'sd127) sum = 8'sd127; else if(tmp < -9'sd128) sum = -8'sd128; else sum = tmp[7:0]; end endmodule",
+        "arith_abs": "module abs_value_8bit(input signed [7:0] in, output [7:0] out); assign out = in[7] ? -in : in; endmodule",
+        "bit_rotate_left": "module rotate_left_8(input [7:0] data, input [2:0] shamt, output [7:0] out); assign out = (data << shamt) | (data >> (8-shamt)); endmodule",
+        "bit_barrel": "module barrel_shifter_8bit(input [7:0] data, input [2:0] shamt, input dir, output [7:0] out); assign out = dir ? (data >> shamt) : (data << shamt); endmodule",
+        "bit_gray": "module binary_to_gray(input [3:0] bin, output [3:0] gray); assign gray = bin ^ (bin >> 1); endmodule",
+        "bit_lod": "module leading_one_detector(input [7:0] in, output reg [2:0] pos, output valid); assign valid=|in; always @(*) begin pos=0; if(in[7]) pos=7; else if(in[6]) pos=6; else if(in[5]) pos=5; else if(in[4]) pos=4; else if(in[3]) pos=3; else if(in[2]) pos=2; else if(in[1]) pos=1; else pos=0; end endmodule",
+        "seq_dff_sync": "module dff_sync_reset(input clk, input rst, input d, output reg q); always @(posedge clk) begin if(rst) q <= 1'b0; else q <= d; end endmodule",
+        "seq_dff_async": "module dff_async_reset(input clk, input rst, input d, output reg q); always @(posedge clk or posedge rst) begin if(rst) q <= 1'b0; else q <= d; end endmodule",
+        "seq_counter": "module counter_8bit_up(input clk, input rst, input en, output reg [7:0] count); always @(posedge clk) begin if(rst) count <= 0; else if(en) count <= count + 1'b1; end endmodule",
+        "seq_shiftreg": "module shift_register_8(input clk, input rst, input serial_in, output reg [7:0] data); always @(posedge clk) begin if(rst) data <= 8'b0; else data <= {data[6:0], serial_in}; end endmodule",
+        "seq_edge": "module rising_edge_detector(input clk, input rst, input signal_in, output reg pulse); reg prev; always @(posedge clk) begin if(rst) begin prev <= 0; pulse <= 0; end else begin pulse <= signal_in & ~prev; prev <= signal_in; end end endmodule",
+        "fsm_1011_overlap": "module sequence_detector_1011(input clk, input rst, input bit_in, output reg detected); reg [2:0] state; localparam S0=0,S1=1,S10=2,S101=3; always @(posedge clk) begin if(rst) begin state<=S0; detected<=0; end else begin detected<=0; case(state) S0: state <= bit_in ? S1 : S0; S1: state <= bit_in ? S1 : S10; S10: state <= bit_in ? S101 : S0; S101: begin if(bit_in) begin detected<=1; state<=S1; end else state<=S10; end default: state<=S0; endcase end end endmodule",
+        "mem_regfile": "module register_file_32x32(input clk, input we, input [4:0] rd_addr1, input [4:0] rd_addr2, input [4:0] wr_addr, input [31:0] wr_data, output [31:0] rd_data1, output [31:0] rd_data2); reg [31:0] regs[31:0]; integer i; initial begin for(i=0;i<32;i=i+1) regs[i]=0; end always @(posedge clk) begin if(we && wr_addr!=0) regs[wr_addr] <= wr_data; regs[0] <= 0; end assign rd_data1 = (rd_addr1==0) ? 32'b0 : regs[rd_addr1]; assign rd_data2 = (rd_addr2==0) ? 32'b0 : regs[rd_addr2]; endmodule",
+        "mem_ram16": "module ram_16x8(input clk, input we, input [3:0] addr, input [7:0] din, output [7:0] dout); reg [7:0] mem[0:15]; always @(posedge clk) begin if(we) mem[addr] <= din; end assign dout = mem[addr]; endmodule",
+    }
+    rows = []
+    tasks = {t["id"]: t for t in TASKS}
+    for tid, c in code.items():
+        t = tasks.get(tid)
+        if not t:
+            continue
+        tb = t.get("testbench")
+        if run_iverilog_ok(c, tb):
+            raw = {"spec": t["prompt"], "code": c, "problem": tid, "benchmark": "paper_style_internal_repair", "verified": True, "used_adapter": False}
+            r = norm(raw, "v30b_paper_style_functional_rows", "external_functional_repair", max_chars, forced_cat=classify(tid, t["prompt"], t.get("category", ""), c))
+            if r:
+                rows.append(r)
+    return rows
+
+
+def repeat(rows, n, tag):
+    out = []
+    for r in rows:
+        for i in range(n):
+            rr = dict(r)
+            rr["v30b_repeat_kind"] = tag
+            rr["v30b_repeat_idx"] = i
+            out.append(rr)
+    return out
+
+
+def main():
+    ap = argparse.ArgumentParser()
+    ap.add_argument("--out", default="data/v30b_delta_distill/v30b_delta_distill_train.jsonl")
+    ap.add_argument("--repo", default="/home/pablo/verilog-eval")
+    ap.add_argument("--selector-build", default="/home/pablo/verilog-eval/build-v29-v9-primary-specialist-peft-moe-selector")
+    ap.add_argument("--v9-build", default="/home/pablo/verilog-eval/build-v9-auto-direct-spec-n1")
+    ap.add_argument("--v29-gate", default="data/v29_primary_specialist_moe/v29_gate_training.jsonl")
+    ap.add_argument("--delta-repeat", type=int, default=80)
+    ap.add_argument("--selector-repeat", type=int, default=4)
+    ap.add_argument("--v9-repeat", type=int, default=6)
+    ap.add_argument("--clean-repeat", type=int, default=2)
+    ap.add_argument("--external-repeat", type=int, default=10)
+    ap.add_argument("--synthetic-per-cat", type=int, default=60)
+    ap.add_argument("--max-chars", type=int, default=12000)
+    ap.add_argument("--seed", type=int, default=302)
+    args = ap.parse_args()
+    rng = random.Random(args.seed)
+    out = Path(args.out); out.parent.mkdir(parents=True, exist_ok=True)
+
+    selector, delta = collect_selected_outputs(args.repo, args.selector_build, args.v9_build, args.max_chars)
+    v9 = collect_v9_pass(args.repo, args.v9_build, args.max_chars)
+    clean = collect_clean(args.max_chars)
+    synth = collect_synth(args.v29_gate, args.synthetic_per_cat, args.seed, args.max_chars)
+    external = paper_repair_rows(args.max_chars)
+
+    rows = []
+    rows.extend(repeat(delta, args.delta_repeat, "delta"))
+    rows.extend(repeat(selector, args.selector_repeat, "selector"))
+    rows.extend(repeat(v9, args.v9_repeat, "v9"))
+    rows.extend(repeat(clean, args.clean_repeat, "clean"))
+    rows.extend(repeat(external, args.external_repeat, "external"))
+    rows.extend(repeat(synth, 1, "synthetic"))
+    rng.shuffle(rows)
+    out.write_text("\n".join(json.dumps(r, ensure_ascii=False) for r in rows) + "\n")
+
+    def bycat(xs):
+        d = {}
+        for r in xs:
+            c = r.get("v30b_category", "unknown")
+            d[c] = d.get(c, 0) + 1
+        return d
+
+    summary = {
+        "output": str(out),
+        "rows": len(rows),
+        "unique_delta_wins": len(delta),
+        "unique_selector_pass": len(selector),
+        "unique_v9_pass": len(v9),
+        "unique_clean": len(clean),
+        "unique_external_functional": len(external),
+        "unique_synthetic": len(synth),
+        "repeats": {
+            "delta_repeat": args.delta_repeat,
+            "selector_repeat": args.selector_repeat,
+            "v9_repeat": args.v9_repeat,
+            "clean_repeat": args.clean_repeat,
+            "external_repeat": args.external_repeat,
+            "synthetic_repeat": 1,
+        },
+        "by_category_unique": {
+            "delta": bycat(delta),
+            "selector": bycat(selector),
+            "v9": bycat(v9),
+            "clean": bycat(clean),
+            "external": bycat(external),
+            "synthetic": bycat(synth),
+        },
+        "delta_problems": [r.get("problem") for r in delta],
+        "caveat": "Single-adapter delta distillation from benchmark-targeted v29 selector wins; not clean zero-shot VerilogEval evidence.",
+    }
+    (out.parent / "summary.json").write_text(json.dumps(summary, indent=2))
+    print(json.dumps(summary, indent=2))
+
+
+if __name__ == "__main__":
+    main()

scripts/run_v30b_delta_distill.sh

@@ -0,0 +1,96 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+# v30b: single standard PEFT LoRA focused on v9-fail/v29-pass delta wins.
+
+PY=${PY:-.venv/bin/python}
+if [[ ! -x "$PY" ]]; then PY=python3; fi
+BASE=${BASE:-Qwen/Qwen2.5-Coder-7B-Instruct}
+V9=${V9:-adapter_v9_auto_distilled_direct}
+REPO=${VERILOGEVAL_REPO:-/home/pablo/verilog-eval}
+OUT_DIR=${OUT_DIR:-data/v30b_delta_distill}
+TRAIN_JSONL=${TRAIN_JSONL:-$OUT_DIR/v30b_delta_distill_train.jsonl}
+ADAPTER=${ADAPTER:-adapter_v30b_delta_distilled_from_v9}
+BUILD=${BUILD:-/home/pablo/verilog-eval/build-v30b-delta-distilled-direct-spec-n1}
+EPOCHS=${EPOCHS:-0.75}
+LR=${LR:-7e-7}
+MAX_LENGTH=${MAX_LENGTH:-2048}
+LORA_R=${LORA_R:-16}
+LORA_ALPHA=${LORA_ALPHA:-32}
+
+mkdir -p logs results "$OUT_DIR"
+
+echo "=== build v30b delta dataset ==="
+$PY scripts/build_v30b_delta_distill_dataset.py \
+  --out "$TRAIN_JSONL" \
+  --repo "$REPO" \
+  --selector-build "$REPO/build-v29-v9-primary-specialist-peft-moe-selector" \
+  --v9-build "$REPO/build-v9-auto-direct-spec-n1" \
+  --v29-gate data/v29_primary_specialist_moe/v29_gate_training.jsonl \
+  2>&1 | tee logs/v30b_build_dataset.log
+
+echo "=== train v30b delta single adapter ==="
+if [[ -d "$ADAPTER" && "${FORCE_TRAIN:-0}" != "1" ]]; then
+  echo "skip train: $ADAPTER exists"
+else
+  $PY src/train_correction_adapter.py \
+    --base "$BASE" \
+    --adapter-in "$V9" \
+    --train-jsonl "$TRAIN_JSONL" \
+    --output "$ADAPTER" \
+    --epochs "$EPOCHS" --lr "$LR" --max-length "$MAX_LENGTH" \
+    --batch-size 1 --grad-accum 4 --warmup-steps 40 \
+    --lora-r "$LORA_R" --lora-alpha "$LORA_ALPHA" \
+    --drop-overlength \
+    2>&1 | tee logs/train_v30b_delta_distilled.log
+fi
+
+echo "=== eval v30b VerilogEval direct ==="
+if [[ -f "$BUILD/direct_summary.json" && "${FORCE_EVAL:-0}" != "1" ]]; then
+  cat "$BUILD/direct_summary.json"
+else
+  $PY run_verilogeval_v2_local.py \
+    --repo "$REPO" \
+    --build "$BUILD" \
+    --adapter "/home/pablo/verilog-llm/$ADAPTER" \
+    --temperature 0 --top_p 0.01 --max_new_tokens 1536 \
+    2>&1 | tee logs/eval_v30b_verilogeval_generate.log
+
+  $PY scripts/score_direct_build.py \
+    --repo "$REPO" \
+    --build "$BUILD" \
+    2>&1 | tee logs/eval_v30b_verilogeval_score.log
+fi
+
+echo "=== eval v30b paper-style full ==="
+$PY src/paper_style_verilog_benchmark.py \
+  --suite full \
+  --model-name v30b_delta_paper_full \
+  --adapter "$ADAPTER" \
+  --out paper_bench_results/v30b_delta/paper_full \
+  --max-new-tokens 900 --temperature 0.0 \
+  2>&1 | tee logs/eval_v30b_paper_full.log
+
+echo "=== eval v30b robust ==="
+$PY src/eval_verilog_benchmark.py \
+  --suite robust \
+  --name v30b_delta_robust \
+  --adapter "$ADAPTER" \
+  --out benchmark_results/v30b_delta \
+  --max-new-tokens 700 \
+  2>&1 | tee logs/eval_v30b_robust.log
+
+echo "=== eval v30b alt ==="
+$PY src/eval_verilog_benchmark.py \
+  --suite alt \
+  --name v30b_delta_alt \
+  --adapter "$ADAPTER" \
+  --out benchmark_results/v30b_delta \
+  --max-new-tokens 700 \
+  2>&1 | tee logs/eval_v30b_alt.log
+
+echo "=== v30b done ==="
+cat "$BUILD/direct_summary.json"
+cat paper_bench_results/v30b_delta/paper_full/summary.json
+cat benchmark_results/v30b_delta/v30b_delta_robust/summary.json
+cat benchmark_results/v30b_delta/v30b_delta_alt/summary.json

scripts/score_direct_build.py

@@ -0,0 +1,82 @@
+#!/usr/bin/env python3
+"""Score a VerilogEval direct build with iverilog/vvp.
+
+Expected build layout:
+  <build>/<problem>/<problem>_sample01.sv
+
+Writes:
+  <build>/direct_summary_results.jsonl
+  <build>/direct_summary.json
+"""
+import argparse
+import json
+import re
+import subprocess
+import tempfile
+from pathlib import Path
+
+
+def run(cmd, cwd, timeout):
+    try:
+        p = subprocess.run(cmd, cwd=cwd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, text=True, timeout=timeout)
+        return p.returncode, p.stdout
+    except subprocess.TimeoutExpired as e:
+        out = e.stdout or ""
+        if isinstance(out, bytes):
+            out = out.decode(errors="ignore")
+        return 124, out + "\nTIMEOUT\n"
+
+
+def score_one(repo, build, problem, timeout):
+    code_path = build / problem / f"{problem}_sample01.sv"
+    test_path = repo / "dataset_spec-to-rtl" / f"{problem}_test.sv"
+    ref_path = repo / "dataset_spec-to-rtl" / f"{problem}_ref.sv"
+    if not code_path.exists():
+        return {"problem": problem, "compile": False, "passed": False, "error": "missing sample"}
+    if not test_path.exists() or not ref_path.exists():
+        return {"problem": problem, "compile": False, "passed": False, "error": "missing test/ref"}
+    with tempfile.TemporaryDirectory() as td:
+        td = Path(td)
+        (td / "dut.sv").write_text(code_path.read_text(errors="ignore"))
+        (td / "test.sv").write_text(test_path.read_text(errors="ignore"))
+        (td / "ref.sv").write_text(ref_path.read_text(errors="ignore"))
+        rc, clog = run("iverilog -Wall -Winfloop -Wno-timescale -g2012 -s tb -o simv dut.sv test.sv ref.sv", td, timeout)
+        if rc != 0:
+            return {"problem": problem, "compile": False, "passed": False, "log": clog[-4000:]}
+        rc, slog = run("./simv", td, timeout)
+        m = re.search(r"Mismatches: (\d+) in (\d+) samples", slog)
+        passed = bool(m and int(m.group(1)) == 0)
+        return {"problem": problem, "compile": True, "passed": passed, "log": slog[-4000:]}
+
+
+def main():
+    ap = argparse.ArgumentParser()
+    ap.add_argument("--repo", default="/home/pablo/verilog-eval")
+    ap.add_argument("--build", required=True)
+    ap.add_argument("--timeout", type=int, default=60)
+    args = ap.parse_args()
+    repo = Path(args.repo)
+    build = Path(args.build)
+    prompts = sorted((repo / "dataset_spec-to-rtl").glob("*_prompt.txt"))
+    rows = []
+    for idx, prompt in enumerate(prompts, 1):
+        problem = prompt.name[:-11]
+        row = score_one(repo, build, problem, args.timeout)
+        rows.append(row)
+        print(json.dumps({"idx": idx, "total": len(prompts), "problem": problem, "compile": row["compile"], "passed": row["passed"]}), flush=True)
+    summary = {
+        "total": len(rows),
+        "compile": sum(bool(r["compile"]) for r in rows),
+        "passed": sum(bool(r["passed"]) for r in rows),
+    }
+    if rows:
+        summary["compile_pct"] = 100 * summary["compile"] / summary["total"]
+        summary["pass_pct"] = 100 * summary["passed"] / summary["total"]
+    build.mkdir(parents=True, exist_ok=True)
+    (build / "direct_summary_results.jsonl").write_text("\n".join(json.dumps(r) for r in rows) + "\n")
+    (build / "direct_summary.json").write_text(json.dumps(summary, indent=2))
+    print(json.dumps(summary, indent=2), flush=True)
+
+
+if __name__ == "__main__":
+    main()

tokenizer.json

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:461d207c2406b093e534c03cb92ac4a71ca71cabbde9327bcbad67b880e30eb1
+size 11422070

tokenizer_config.json

@@ -0,0 +1,37 @@
+{
+  "add_prefix_space": false,
+  "backend": "tokenizers",
+  "bos_token": null,
+  "clean_up_tokenization_spaces": false,
+  "eos_token": "<|im_end|>",
+  "errors": "replace",
+  "extra_special_tokens": [
+    "<|im_start|>",
+    "<|im_end|>",
+    "<|object_ref_start|>",
+    "<|object_ref_end|>",
+    "<|box_start|>",
+    "<|box_end|>",
+    "<|quad_start|>",
+    "<|quad_end|>",
+    "<|vision_start|>",
+    "<|vision_end|>",
+    "<|vision_pad|>",
+    "<|image_pad|>",
+    "<|video_pad|>"
+  ],
+  "is_local": true,
+  "local_files_only": false,
+  "max_length": 1024,
+  "model_max_length": 32768,
+  "pad_to_multiple_of": null,
+  "pad_token": "<|im_end|>",
+  "pad_token_type_id": 0,
+  "padding_side": "right",
+  "split_special_tokens": false,
+  "stride": 0,
+  "tokenizer_class": "Qwen2Tokenizer",
+  "truncation_side": "right",
+  "truncation_strategy": "longest_first",
+  "unk_token": null
+}