---
language:
- en
license: apache-2.0
tags:
- evaluation
- Verilog
- code
task_categories:
- text-generation
dataset_info:
  features:
  - name: task
    dtype: string
  - name: question
    dtype: string
  - name: answer
    dtype: string
  - name: testbench
    dtype: string
  splits:
  - name: train
    num_bytes: 730092
    num_examples: 156
  download_size: 158613
  dataset_size: 730092
configs:
- config_name: default
  data_files:
  - split: train
    path: data/train-*
---
# VerilogEval-v2-NTU

This repository provides the patched version of VerilogEval-v2's dataset_spec-to-rtl, a benchmark designed to evaluate the capabilities of large language models in digital design and hardware description languages. The original VerilogEval-v2 dataset was developed by NVLabs and is available at https://github.com/NVlabs/verilog-eval under the MIT License.

All patches are located in the `patches` directory and are generated by `create_patch.sh`. The file `data/train-00000-of-00001.parquet` contains the patched dataset, which also includes the unmodified problems.

## Patches Descriptions

- Initialization and Reset Handling: We removed non-synthesizable initial blocks from all reference designs. To ensure proper register initialization, we introduced an explicit reset signal and updated the corresponding problem prompts.
  - Patched Problems: 34, 53, 66, 104
- Synthesizability and Logic Corrections: In several problems, the reference designs produced unsynthesizable high-impedance or undefined outputs. We rewrote these modules to adhere to standard synthesizable SystemVerilog conventions.
  - Patched Problems: 116, 124, 151, 156
- Specification Alignment and Disambiguation: We resolved inconsistencies between prompts and implementations. For Problem 62, the module logic was corrected to match the selection requirement (selecting a or b when sel is 1). For Problem 63, we explicitly defined the shift register's direction in the prompt to eliminate ambiguity.
  - Patched Problems: 62, 63
- FSM and Interface Refinement: For problems involving Finite State Machines (FSMs) and complex interfaces, we refined the descriptions to clarify state transition conditions and port declarations, removing extraneous information.
  - Patched Problems: 89, 93, 123, 134
- Naming Standardization: We corrected naming inconsistencies to ensure uniform testing. This includes fixing port mappings in Problem 99 (correcting Y2/Y4 to Y3/Y1) and resolving top-module naming issues in Problem 131.
  - Patched Problems: 99, 131

## Acknowledgments

We thank Wei-Po Hsin and experienced IC engineers for identifying and addressing issues in the original dataset. The patches descriptions are sourced from the paper titled "EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization," available at https://arxiv.org/abs/2601.18067.

## License

The patched content in this repository is licensed under the Apache License 2.0. See the LICENSE file for details. The original dataset is licensed under the MIT License. A copy of this license is included in this repository; see VerilogEval-v2-LICENSE for details.