Hugging Face's logo

Datasets:
pcy12345BSU
/
sleigh_instru_combined

Modalities:
Text
Formats:
csv
Size:
< 1K
Libraries:
Datasets
pandas
Dataset card Data Studio Files
xet
 Community
1
sleigh_instru_combined / sleighInstucJsonFile_combineFile_.csv
pcy12345BSU's picture
pcy12345BSU
Upload sleighInstucJsonFile_combineFile_.csv
a4335f3 verified
Raw
History Blame Contribute Delete
259 kB
format,code,abstract,description,operation
"dct pinc Sx,Dz",111110********** 10011010xx00zzzz,"If DC = 1: MSW of Sx + 1 -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pinc_sx_dct (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"dcf pcopy Sx,Dz",111110********** 11011011xx00zzzz,If DC = 0: Sx -> Dz Else: nop,"Conditionally stores the Sx operand in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pcopy_sx_dcf (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_SRC2 = 0;
 DSP_ALU_SRC2G = 0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"ldbank @Rm,R0",0100mmmm11100101,(Specified register bank entry) -> R0,The register bank entry indicated by the contents of general register Rm is transferred to general register R0. The register bank number and register stored in the bank are specified by general register Rm.,"void LDBANK (int m) {
 R[0] = Read_Bank_32 (R[m]);
 PC += 2;
}"
"ldc Rm,SR",0100mmmm00001110,Rm -> SR,Stores the source operand in the control register SR.,"void LDCSR (int m) {
 #if SH1 || SH2 || SH2 || SH3
 SR = R[m] & 0x0FFF0FFF;
 #elif SH2A
 SR = R[m] & 0x000063F3;
 #elif SH4 || SH4A
 SR = R[m] & 0x700083F3;
 #endif
 PC += 2;
}"
"ldc.l @Rm+,SR",0100mmmm00000111,"(Rm) -> SR, Rm+4 -> Rm",Stores the source operand in the control register SR.,"void LDCMSR (int m) {
 #if SH1 || SH2 || SH2 || SH3
 SR = Read_32 (R[m]) & 0x0FFF0FFF;
 #elif SH2A
 SR = Read_32 (R[m]) & 0x000063F3;
 #elif SH4 || SH4A
 SR = Read_32 (R[m]) & 0x700083F3;
 #endif
 R[m] += 4;
 PC += 2;
}"
"ldc Rm,TBR",0100mmmm01001010,Rm -> TBR,Stores a source operand in control register TBR.,"void LDCTBR (int m) {
 TBR = R[m];
 PC += 2;
}"
"ldc Rm,GBR",0100mmmm00011110,Rm -> GBR,Stores a source operand in control register GBR.,"void LDCGBR (int m) {
 GBR = R[m];
 PC += 2;
}"
"ldc.l @Rm+,GBR",0100mmmm00010111,"(Rm) -> GBR, Rm+4 -> Rm",Stores a source operand in control register GBR.,"void LDCMGBR (int m) {
 GBR = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"ldc Rm,VBR",0100mmmm00101110,Rm -> VBR,Stores a source operand in control register VBR.,"void LDCVBR (int m) {
 VBR = R[m];
 PC += 2;
}"
"fmul FRm,FRn",1111nnnnmmmm0010,FRn * FRm -> FRn,"Arithmetically multiplies the two single-precision floating-point numbers in FRn and FRm, and stores the result in FRn.","void FMUL (int m, int n) {
 PC += 2;
 clear_cause ();
 if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
 invalid (n);
 else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
 qnan (n);
 else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
 set_E ();
 else
 switch (data_type_of (m))
 {
 case NORM:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 zero (n, sign_of (m) ^ sign_of (n));
 break;
 case PINF:
 case NINF:
 inf (n, sign_of (m) ^ sign_of (n));
 break;
 default:
 normal_fmul (m, n);
 break;
 }
 break;
 case PZERO:
 case NZERO:
 switch (data_type_of (n))
 {
 case PINF:
 case NINF:
 invalid (n);
 break;
 default:
zero (n,sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 case PINF:
 case NINF:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 invalid (n);
 break;
 default:
 inf (n, sign_of (m) ^ sign_of (n));
 break
 }
 break;
 }
}"
"movx.w @Ax,Dx",111100A*D*0*01**,"(Ax) -> MSW of Dx, 0 -> LSW of Dx",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for X memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,"MOVX.W @R4,X0 ! Before execution: R4 = 0x08010000, @R4 = 0x5555, X0 = 0x12345678
 ! After execution: R4 = 0x08010000, X0 = 0x55550000"
"movx.w @Ax+,Dx",111100A*D*0*10**,"(Ax) -> MSW of Dx, 0 -> LSW of Dx, Ax+2 -> Ax",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for X memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,"MOVX.W @R4+,X0 ! Before execution: R4 = 0x08010000, @R4 = 0x5555, X0 = 0x12345678
 ! After execution: R4 = 0x08010002, X0 = 0x55550000"
"movx.w @Ax+Ix,Dx",111100A*D*0*11**,"(Ax) -> MSW of Dx, 0 -> LSW of Dx, Ax+Ix -> Ax",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for X memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,
"movx.w Da,@Ax",111100A*D*1*01**,MSW of Da -> (Ax),Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register.,
"movx.w Da,@Ax+",111100A*D*1*10**,"MSW of Da -> (Ax), Ax+2 -> Ax",Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register.,
"movx.w Da,@Ax+Ix",111100A*D*1*11**,"MSW of Da -> (Ax), Ax+Ix -> Ax",Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register.,
nopy,111100*0*0*0**00,No Operation,No access operation for Y memory.,
"ldc.l @Rm+,DBR",0100mmmm11110110,"(Rm) -> DBR, Rm+4 -> Rm",Stores a source operand in control register DBR.,"void LDCMDBR (int m) {
 DBR = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"ldc Rm,Rn_BANK",0100mmmm1nnn1110,Rm -> Rn_BANK (n = 0-7),"Stores a source operand in banked general register. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.","void LDCRn_BANK (int m) {
 Rn_BANK = R[m];
 PC += 2;
}"
"ldc.l @Rm+,Rn_BANK",0100mmmm1nnn0111,"(Rm) -> Rn_BANK, Rm+4 -> Rm","Stores a source operand in banked general register. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.","void LDCMRn_BANK (int m) {
 Rn_BANK = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"ldre @(disp,PC)",10001110dddddddd,disp*2 + PC -> RE,"Stores the effective address of the source operand in the repeat end register RE. The effective address is an address specified by PC + displacement. The PC is the address four bytes after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the relative interval from the branch destination is -256 to +254 bytes.","void LDRE (int d) {
 long disp;
 if ((d & 0x80) == 0)
 disp = (0x000000FF & (long)d);
 else
 disp = (0xFFFFFF00 | (long)d);
 RE = PC + (disp << 1);
 PC += 2;
}"
"ldrs @(disp,PC)",10001100dddddddd,disp*2 + PC -> RS,"Stores the effective address of the source operand in the repeat start register RS. The effective address is an address specified by PC + displacement. The PC is the address four bytes after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the relative interval from the branch destination is -256 to +254 bytes.","void LDRS (int d) {
 long disp;
 if ((d & 0x80) == 0)
 disp = (0x000000FF & (long)d);
 else
 disp = (0xFFFFFF00 | (long)d);
 RS = PC + (disp << 1);
 PC += 2;
}"
"lds Rm,MACH",0100mmmm00001010,Rm -> MACH,Stores the source operand into the system register MACH.,"void LDSMACH (int m) {
 MACH = R[m];
 #if SH1
 if ((MACH & 0x00000200) == 0)
 MACH &= 0x000003FF;
else
 MACH |= 0xFFFFFC00;
 #endif
 PC += 2;
}"
"lds.l @Rm+,MACH",0100mmmm00000110,"(Rm) -> MACH, Rm+4 -> Rm",Stores the source operand into the system register MACH.,"void LDSMMACH (int m) {
 MACH = Read_32 (R[m]);
 #if SH1
 if ((MACH & 0x00000200) == 0)
 MACH &= 0x000003FF;
else
 MACH |= 0xFFFFFC00;
 #endif
 R[m] += 4;
 PC += 2;
}"
"movy.w @Ay,Dy",111100*A*D*0**01,"(Ay) -> MSW of Dy, 0 -> LSW of Dy",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,
"movy.w @Ay+,Dy",111100*A*D*0**10,"(Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+2 -> Ay",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,
"movy.w @Ay+Iy,Dy",111100*A*D*0**11,"(Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+Iy -> Ay",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,
"movy.w Da,@Ay",111100*A*D*1**01,MSW of Da -> (Ay),Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register.,
"movy.w Da,@Ay+",111100*A*D*1**10,"MSW of Da -> (Ay), Ay+2 -> Ay",Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register.,
"pinc Sy,Dz",111110********** 1011100100yyzzzz,"MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz","Adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pinc_sy (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 #include ""integer_unconditional_update.c""
 #include ""integer_plus_dc_bit.c""
}"
"pdec Sx,Dz",111110********** 10001001xx00zzzz,"MSW of Sx - 1 -> MSW of Dz, clear LSW of Dz","Subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pdec_sx (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 #include ""integer_unconditional_update.c""
 #include ""integer_minus_dc_bit.c""
}"
"movy.w @Ay,Dy",111100*A*D*0**01,"(Ay) -> MSW of Dy, 0 -> LSW of Dy",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,
"movy.w @Ay+,Dy",111100*A*D*0**10,"(Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+2 -> Ay",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,
"movy.w @Ay+Iy,Dy",111100*A*D*0**11,"(Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+Iy -> Ay",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,
"movy.w Da,@Ay",111100*A*D*1**01,MSW of Da -> (Ay),Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register.,
"movy.w Da,@Ay+",111100*A*D*1**10,"MSW of Da -> (Ay), Ay+2 -> Ay",Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register.,
"movy.w Da,@Ay+Iy",111100*A*D*1**11,"MSW of Da -> (Ay), Ay+Iy -> Ay",Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register.,
"movs.w @-As,Ds",111101AADDDD0000,"As-2 -> As, (As) -> MSW of Ds, 0 -> LSW of Ds","Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"exts.w Rm,Rn",0110nnnnmmmm1111,Rm sign-extended from word -> Rn,Sign-extends the contents of general register Rm and stores the result in Rn. The value of Rm bit 15 is transferred to Rn bits 16 to 31.,"void EXTSW (int m, int n) {
 R[n] = R[m];
 if ((R[m] & 0x00008000) == 0)
 R[n] & = 0x0000FFFF;
 else
 R[n] |= 0xFFFF0000;
 PC += 2;
}"
"extu.b Rm,Rn",0110nnnnmmmm1100,Rm zero-extended from byte -> Rn,Zero-extends the contents of general register Rm and stores the result in Rn. 0 is transferred to Rn bits 8 to 31.,"void EXTUB (int m, int n) {
 R[n] = R[m];
 R[n] &= 0x000000FF;
 PC += 2;
}"
"extu.w Rm,Rn",0110nnnnmmmm1101,Rm zero-extended from word -> Rn,Zero-extends the contents of general register Rm and stores the result in Rn. 0 is transferred to Rn bits 16 to 31.,"void EXTUW (int m, int n) {
 R[n] = R[m];
 R[n] &= 0x0000FFFF;
 PC += 2;
}"
"mac.l @Rm+,@Rn+",0000nnnnmmmm1111,"Signed, (Rn) * (Rm) + MAC -> MAC 32 * 32 + 64 -> 64 bits","Performs signed multiplication of the 32-bit operands whose addresses are the contents of general registers Rm and Rn, adds the 64-bit result to the MAC register contents, and stores the result in the MAC register. Operands Rm and Rn are each incremented by 4 each time they are read. When the S bit is cleared to 0, the 64-bit result is stored in the coupled MACH and MACL registers. When bit S is set to 1, addition to the MAC register is a saturation operation of 48 bits starting from the LSB. For the saturation operation, only the lower 48 bits of the MACL register are enabled and the result is limited to a range of 0xFFFF800000000000 (minimum) and 0x00007FFFFFFFFFFF (maximum).","void MACL (int m, int n) {
 unsigned long RnL, RnH, RmL, RmH, Res0, Res1, Res2;
 unsigned long temp0, temp1, temp2, temp3;
 long tempm, tempn, fnLmL;
 tempn = Read_32 (R[n]);
 R[n] += 4;
 tempm = Read_32 (R[m]);
 R[m] += 4;
 if ((long)(tempn ^ tempm) < 0)
 fnLmL = -1;
 else
 fnLmL = 0;
 if (tempn < 0)
 tempn = 0 - tempn;
 if (tempm < 0)
 tempm = 0 - tempm;
 temp1 = (unsigned long)tempn;
 temp2 = (unsigned long)tempm;
 RnL = temp1 & 0x0000FFFF;
 RnH = (temp1 >> 16) & 0x0000FFFF;
 RmL = temp2 & 0x0000FFFF;
 RmH = (temp2 >> 16) & 0x0000FFFF;
 temp0 = RmL * RnL;
 temp1 = RmH * RnL;
 temp2 = RmL * RnH;
 temp3 = RmH * RnH;
 Res2 = 0;
 Res1 = temp1 + temp2;
 if (Res1 < temp1)
 Res2 += 0x00010000;
 temp1 = (Res1 << 16) & 0xFFFF0000;
 Res0 = temp0 + temp1;
 if (Res0 < temp0)
 Res2++;
 Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3;
 if(fnLmL < 0)
 {
 Res2 = ~Res2;
 if (Res0 == 0)
 Res2++;
 else
 Res0 = (~Res0) + 1;
 }
 if (S == 1)
 {
 Res0 = MACL + Res0;
 if (MACL > Res0)
 Res2++;
 Res2 += MACH & 0x0000FFFF;
 if (((long)Res2 < 0) && (Res2 < 0xFFFF8000))
 {
 Res2 = 0xFFFF8000;
 Res0 = 0x00000000;
 }
 if (((long)Res2 > 0) && (Res2 > 0x00007FFF))
 {
 Res2 = 0x00007FFF;
 Res0 = 0xFFFFFFFF;
 }
 MACH = (Res2 & 0x0000FFFF) | (MACH & 0xFFFF0000);
 MACL = Res0;
 }
 else
 {
 Res0 = MACL + Res0;
 if (MACL > Res0)
 Res2 ++;
 Res2 += MACH;
 MACH = Res2;
 MACL = Res0;
 }
 PC += 2;
}"
"fcmp/eq DRm,DRn",1111nnn0mmm00100,"If DRn = DRm: 1 -> T
Else: 0 -> T","Arithmetically compares the two double-precision floating-point numbers in DRn and DRm, and stores 1 in the T bit if they are equal, or 0 otherwise.","void FCMP_EQ (int m, int n)
{
 PC += 2;
 clear_cause ();
 if (fcmp_chk_double (m, n) == INVALID)
 fcmp_invalid ();
 else if (fcmp_chk_double (m, n) == EQ)
 T = 1;
 else
 T = 0;
}
int fcmp_chk_double (int m, int n)
{
 if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
 return INVALID;
 else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
 return UO;
 else
 switch (data_type_of (m))
 {
 case NORM:
 switch (data_type_of (n))
 {
 case PINF:
 return GT;
 case NINF:
 return LT;
 default:
 break;
 }
 break;
 case PZERO:
 case NZERO:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 return EQ;
 default:
 break;
 }
 break;
 case PINF:
 switch (data_type_of (n))
 {
 case PINF:
 return EQ;
 default:
 return LT;
 }
 case NINF:
 switch (data_type_of (n))
 {
 case NINF:
 return EQ;
 default:
 return GT;
 }
 }
 if (DR[n >> 1] == DR[m >> 1])
 return EQ;
 else if (DR[n >> 1] > DR[m >> 1])
 return GT;
 else
 return LT;
}
void fcmp_invalid (void)
{
 set_V ();
 if ((FPSCR & ENABLE_V) == 0)
 T = 0;
 else
 fpu_exception_trap ();
}"
"pdec Sy,Dz",111110********** 1010100100yyzzzz,"MSW of Sy - 1 -> MSW of Dz, clear LSW of Dz","Subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pdec_sy (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 #include ""integer_unconditional_update.c""
 #include ""integer_minus_dc_bit.c""
}"
shlr8 Rn,0100nnnn00011001,Rn >> 8 -> [0 -> Rn],"Logically shifts the contents of general register Rn 8 bits to the right, and stores the result in Rn. The bits shifted out of the operand are discarded.","void SHLR8 (int n) {
 R[n] >>= 8;
 R[n] &= 0x00FFFFFF;
 PC += 2;
}"
shlr16 Rn,0100nnnn00101001,Rn >> 16 -> [0 -> Rn],Logically shifts the contents of general register Rn 16 bits to the right and stores the result in Rn. The bits shifted out of the operand are discarded.,"void SHLR16 (int n) {
 R[n] >>= 16;
 R[n] &= 0x0000FFFF;
 PC += 2;
}"
bf label,10001011dddddddd,"If T = 0: disp*2 + PC + 4 -> PC
Else: nop","This is a conditional branch instruction that references the T bit. The branch is taken if T = 0, and not taken if T = 1. The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BF instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BF instruction.","void BF (int d) {
 int disp;
 if ((d & 0x80) == 0)
 disp = (0x000000FF & d);
 else
 disp = (0xFFFFFF00 | d);
 if (T == 0)
 PC = PC + 4 + (disp << 1);
 else
 PC += 2;
}"
bf/s label,10001111dddddddd,"If T = 0: disp*2 + PC + 4 -> PC
Else: nop
(Delayed branch)","This is a delayed conditional branch instruction that references the T bit. If T = 1, the next instruction is executed and the branch is not taken. If T = 0, the branch is taken after execution of the next instruction.","void BFS (int d) {
 int disp;
 unsigned int temp;
 temp = PC;
 if ((d & 0x80) == 0)
 disp = (0x000000FF & d);
 else
 disp = (0xFFFFFF00 | d);
 if (T == 0)
 PC = PC + 4 + (disp << 1);
 else
 PC += 4;
 Delay_Slot (temp + 2);
}"
bt label,10001001dddddddd,"If T = 1: disp*2 + PC + 4 -> PC
Else: nop","This is a conditional branch instruction that references the T bit. The branch is taken if T = 1, and not taken if T = 0. The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BT instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BT instruction.","void BT (int d) {
 int disp;
 if ((d & 0x80) == 0)
 disp = (0x000000FF & d);
 else
 disp = (0xFFFFFF00 | d);
 if (T == 1)
 PC = PC + 4 + (disp << 1);
 else
 PC += 2;
}"
bt/s label,10001101dddddddd,"If T = 1: disp*2 + PC + 4 -> PC
Else: nop
(Delayed branch)","This is a conditional branch instruction that references the T bit. The branch is taken if T = 1, and not taken if T = 0. The PC source value is the BT/S instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BT/S instruction.","void BTS (int d) {
 int disp;
 unsigned temp;
 temp = PC;
 if ((d & 0x80) == 0)
 disp = (0x000000FF & d);
 else
 disp = (0xFFFFFF00 | d);
 if (T == 1)
 PC = PC + 4 + (disp << 1);
 else
 PC += 4;
 Delay_Slot (temp + 2);
}"
bra label,1010dddddddddddd,"disp*2 + PC + 4 -> PC
(Delayed branch)","This is an unconditional branch instruction. The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BRA instruction address. As the 12-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -4096 to +4094 bytes from the BRA instruction. If the branch destination cannot be reached, this branch can be performed with a JMP instruction.","void BRA (int d) {
 int disp;
 unsigned int temp;
 temp = PC;
 if ((d & 0x800) == 0)
 disp = (0x00000FFF & d);
 else
 disp = (0xFFFFF000 | d);
 PC = PC + 4 + (disp << 1);
 Delay_Slot(temp + 2);
}"
"movs.l Ds,@As+",111101AADDDD1011,"Ds -> (As), As+4 -> As",Transfers the source operand data to the destination. The transferred data is a longword.,
"movs.l Ds,@As+Is",111101AADDDD1111,"Ds -> (As), As+Is -> As",Transfers the source operand data to the destination. The transferred data is a longword.,
"pabs Sx,Dz",111110********** 10001000xx00zzzz,"If Sx >= 0: Sx -> Dz
If Sx < 0: 0 - Sx -> Dz","Finds absolute values. When the Sx operand is positive, the contents of the operand are transferred to the Dz operand. If the value is negative, the value of the Sx operand is subtracted from 0 and stored in the Dz operand.",
"pabs Sy,Dz",111110********** 1010100000yyzzzz,"If Sy >= 0: Sy -> Dz
If Sy < 0: 0 - Sy -> Dz","Finds absolute values. When the Sy operand is positive, the contents of the operand are transferred to the Dz operand. If the value is negative, the value of the Sy operand is subtracted from 0 and stored in the Dz operand.",
"padd Sx,Sy,Dz",111110********** 10110001xxyyzzzz,Sx + Sy -> Dz,Adds the contents of the Sx and Sy operands and stores the result in the Dz operand.,
"dcf pdec Sy,Dz",111110********** 1010101100yyzzzz,"If DC = 0: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop","Conditionally subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pdec_sy_dcf (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"fmov DRm,DRn",1111nnn0mmm01100,DRm -> DRn,Transfers DRm contents to DRn.,"void FMOV_DR (int m, int n) {
 DR[n >> 1] = DR[m >> 1];
 PC += 2;
}"
"fmov DRm,XDn",1111nnn1mmm01100,DRm -> XDn,Transfers DRm contents to XDn.,"void FMOV_DRXD (int m, int n) {
 XD[n >> 1] = DR[m >> 1];
 PC += 2;
}"
"fmov XDm,DRn",1111nnn0mmm11100,XDm -> DRn,Transfers XDm contents to DRn.,"void FMOV_XDDR (int m, int n) {
 DR[n >> 1] = XD[m >> 1];
 PC += 2;
}"
"fmov XDm,XDn",1111nnn1mmm11100,XDm -> XDn,Transfers XDm contents to XDn.,"void FMOV_XDXD (int m, int n) {
 XD[n >> 1] = XD[m >> 1];
 PC += 2;
}"
"fmov.d @Rm,DRn",1111nnn0mmmm1000,(Rm) -> DRn,Transfers contents of memory at address indicated by Rm to DRn.,"void FMOV_LOAD_DR (int m, int n) {
 DR[n >> 1] = Read_64 (R[m]);
 PC += 2;
}"
"fmov.d @Rm,XDn",1111nnn1mmmm1000,(Rm) -> XDn,Transfers contents of memory at address indicated by Rm to XDn.,"void FMOV_LOAD_XD (int m, int n) {
 XD[n >> 1] = Read_64 (R[m]);
 PC += 2;
}"
"fmov.d DRm,@Rn",1111nnnnmmm01010,DRm -> (Rn),Transfers DRm contents to memory at address indicated by Rn.,"void FMOV_STORE_DR (int m, int n) {
 Write_64 (R[n], DR[m >> 1]);
 PC += 2;
}"
pclr Dz,111110********** 100011010000zzzz,0x00000000 -> Dz,"Clears the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The Z bit of the DSR register is set to 1. The N, V, and GT bits are cleared to 0.","void pclr (void) {
 DSP_REG[ex2_dz_no] = 0x0;
 if (ex2_dz_no == 0)
 A0G = 0x0;
 else if (ex2_dz_no == 1)
 A1G = 0x0;
 carry_bit = 0;
 negative_bit = 0;
 zero_bit = 1;
 overflow_bit = 0;
 #include ""fixed_pt_plus_dc_bit.c""
}"
"prnd Sx,Dz",111110********** 10011000xx00zzzz,"Sx + 0x00008000 -> Dz, clear LSW of Dz","Does rounding. Adds the immediate data 0x00008000 to the contents of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of Dz with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void prnd_sx (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST = (DSP_ALU_SRC1 + DSP_ALU_SRC2) & MASKFFFF0000;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_plus_dc_bit.c""
}"
"fsub FRm,FRn",1111nnnnmmmm0001,FRn - FRm -> FRn,"Arithmetically subtracts the single-precision floating-point number in FRm from the single-precision floating-point number in FRn, and stores the result in FRn.","void FSUB (int m, int n) {
 PC += 2;
 clear_cause ();
 if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
 invalid (n);
 else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
 qnan (n);
 else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
 set_E ();
 else
 switch (data_type_of (m))
 {
 case NORM:
 switch (data_type_of (n))
 {
 case NORM:
 normal_faddsub (m, n, SUB);
 break;
 case PZERO:
 case NZERO:
 register_copy (m, n);
 FR[n] = -FR[n];
 break;
 default:
 break;
 }
 break;
 case PZERO:
 break;
 case NZERO:
 switch (data_type_of (n))
 {
 case NZERO:
 zero (n, 0);
 break;
 default:
 break;
 }
 break;
 case PINF:
 switch (data_type_of (n))
 {
 case PINF:
 invalid (n);
 break;
 default:
 inf (n, 1);
 break;
 }
 break;
 case NINF:
 switch (data_type_of (n))
 {
 case NINF:
 invalid (n);
 break;
 default:
 inf (n, 0);
 break;
 }
 break;
 }
}"
"dct pdmsb Sy,Dz",111110********** 1011111000yyzzzz,"If DC = 1: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pdmsb_sy_dct (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
dct pclr Dz,111110********** 100011100000zzzz,"If DC = 1: 0x00000000 -> Dz
Else: nop","Conditionally clears the Dz operand. The instruction is executed when the DC
bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pclr_dct (void)
{
 if (DC == 1)
 DSP_REG[ex2_dz_no] = 0x0;
}"
"fmov.d DRm,@(R0,Rn)",1111nnnnmmm00111,DRm -> (R0 + Rn),Transfers DRm contents to memory at address indicated by (R0 + Rn).,"void FMOV_INDEX_STORE_DR (int m, int n)
{
 Write_64 (R[0] + R[n], DR[m >> 1]);
 PC += 2;
}"
"fmov.d XDm,@(R0,Rn)",1111nnnnmmm10111,XDm -> (R0 + Rn),Transfers XDm contents to memory at address indicated by (R0 + Rn).,"void FMOV_INDEX_STORE_XD (int m, int n)
{
 Write_64 (R[0] + R[n], XD[m >> 1]);
 PC += 2;
}"
"fmov.d @(disp12,Rm),DRn",0011nnn0mmmm0001 0111dddddddddddd,(disp*8 + Rm) -> DRn,Transfers memory contents at the address indicated by (disp + Rn) to DRn.,"void FMOV_INDEX_DISP12_LOAD_DR (int m, int n, int d)
{
 long disp = (0x00000FFF & (long)d);
 DR[n >> 1] = Read_64 (R[m] + (disp << 3));
 PC += 4;
}"
"fmov.d DRm,@(disp12,Rn)",0011nnnnmmm00001 0011dddddddddddd,DRm -> (disp*8 + Rn),Transfers DRm contents to memory at the address indicated by (disp + Rn).,"void FMOV_INDEX_DISP12_STORE_DR (int m, int n, int d)
{
 long disp = (0x00000FFF & (long)d);
 Write_64 (R[n] + (disp << 3), DR[m >> 1]);
 PC += 4;
}"
fldi0 FRn,1111nnnn10001101,0x00000000 -> FRn,"When FPSCR.PR = 0, this instruction loads floating-point 0.0 (0x00000000) into FRn. If FPSCR.PR = 1, the instruction is handled as an illegal instruction.","void FLDI0 (int n)
{
 FR[n] = 0x00000000;
 PC += 2;
}"
fldi1 FRn,1111nnnn10011101,0x3F800000 -> FRn,"When FPSCR.PR = 0, this instruction loads floating-point 1.0 (0x3F800000) into FRn. If FPCSR.PR = 1, the instruction is handled as an illegal instruction.","void FLDI1 (int n)
{
 FR[n] = 0x3F800000;
 PC += 2;
}"
"flds FRm,FPUL",1111mmmm00011101,FRm -> FPUL,Transfers the contents of floating-point register FRm into system register FPUL.,"void FLDS (int m)
{
 FPUL = FR[m];
 PC += 2;
}"
sets,0000000001011000,1 -> S,Sets the S bit to 1.,"void SETS (void)
{
 S = 1;
 PC += 2;
}"
sett,0000000000011000,1 -> T,Sets the T bit to 1.,"void SETT (void)
{
 T = 1;
 PC += 2;
}"
sleep,0000000000011011,Sleep or standby,Places the CPU in the power-down state.,"void SLEEP (void)
{
 Sleep_standby();
}"
"stbank R0,@Rn",0100nnnn11100001,R0 -> (specified register bank entry),R0 is transferred to the register bank entry indicated by the contents of general register Rn.,"void STBANK (int n)
{
 Write_Bank_32 (R[n], R[0])
 PC += 2;
}"
"stc SR,Rn",0000nnnn00000010,SR -> Rn,Stores control register SR in the destination.,"void STCSR (int n)
{
 R[n] = SR;
 PC += 2;
}"
"stc.l SR,@-Rn",0100nnnn00000011,"Rn-4 -> Rn, SR -> (Rn)",Stores control register SR in the destination.,"void STCMSR (int n)
{
 R[n] -= 4;
 Write_32 (R[n], SR);
 PC += 2;
}"
"stc TBR,Rn",0000nnnn01001010,TBR -> Rn,Stores control register TBR in the destination.,"void STCTBR (int n)
{
 R[n] = TBR;
 PC += 2;
}"
"cmp/eq Rm,Rn",0011nnnnmmmm0000,If Rn = Rm: 1 -> T Else: 0 -> T,"Compares general registers Rn and Rm, and sets the T bit if they are equal. The contents of Rn and Rm are not changed.","void CMPEQ (int m, int n) { if (R[n] == R[m]) T = 1; else T = 0; PC += 2; }"
"cmp/hs Rm,Rn",0011nnnnmmmm0010,If Rn >= Rm (unsigned): 1 -> T Else: 0 -> T,"Compares general registers Rn and Rm, and sets the T bit if Rn is greater or equal Rm. The values for the comparison are interpreted as unsigned integer values. The contents of Rn and Rm are not changed.","void CMPHI (int m, int n) { if ((unsigned long)R[n] >= (unsigned long)R[m]) T = 1; else T = 0; PC += 2; }"
"cmp/ge Rm,Rn",0011nnnnmmmm0011,If Rn >= Rm (signed): 1 -> T Else: 0 -> T,"Compares general registers Rn and Rm, and sets the T bit if Rn is greater or equal Rm. The values for the comparison are interpreted as signed integer values. The contents of Rn and Rm are not changed.","void CMPGE (int m, int n) { if ((long)R[n] >= (long)R[m]) T = 1; else T = 0; PC += 2; }"
"cmp/hi Rm,Rn",0011nnnnmmmm0110,If Rn > Rm (unsigned): 1 -> T Else: 0 -> T,"Compares general registers Rn and Rm, and sets the T bit if Rn is greater Rm. The values for the comparison are interpreted as unsigned integer values. The contents of Rn and Rm are not changed.","void CMPHI (int m, int n) { if ((unsigned long)R[n] > (unsigned long)R[m]) T = 1; else T = 0; PC += 2; }"
"cmp/gt Rm,Rn",0011nnnnmmmm0111,If Rn > Rm (signed): 1 -> T Else: 0 -> T,"Compares general registers Rn and Rm, and sets the T bit if Rn is greater Rm. The values for the comparison are interpreted as signed integer values. The contents of Rn and Rm are not changed.","void CMPGT (int m, int n) { if ((long)R[n] > (long)R[m]) T = 1; else T = 0; PC += 2; }"
cmp/pl Rn,0100nnnn00010101,If Rn > 0 (signed): 1 -> T Else: 0 -> T,Compares general register Rn and sets the T bit if Rn is greater 0. The value in Rn for the comparison is interpreted as signed integer. The contents of Rn are not changed.,void CMPPL (int n) { if ((long)R[n] > 0) T = 1; else T = 0; PC += 2; }
cmp/pz Rn,0100nnnn00010001,If Rn >= 0 (signed): 1 -> T Else: 0 -> T,Compares general register Rn and sets the T bit if Rn is greater or equal 0. The value in Rn for the comparison is interpreted as signed integer. The contents of Rn are not changed.,void CMPPZ (int n) { if ((long)R[n] >= 0) T = 1; else T = 0; PC += 2; }
ocbwb @Rn,0000nnnn10110011,Write back operand cache block,"Accesses data using the contents indicated by effective address Rn. If the cache is hit and there is unwritten information (U bit = 1), the corresponding cache block is written back to external memory and that block is cleaned (the U bit is cleared to 0). In other cases (i.e. in the case of a cache miss or an access to a non-cache area, or if the block is already clean), no operation is performed.","void OCBWB (int n) {
 if (is_dirty_block (R[n]))
 write_back (R[n]);
 PC += 2;
}"
pref @Rn,0000nnnn10000011,(Rn) -> operand cache,"SH4 and SH4A: Reads a 32-byte data block starting at a 32-byte boundary into the operand cache. The lower 5 bits of the address specified by Rn are masked to zero. This instruction is also used to trigger a Store Queue write-back operation if the specified address points to the Store Queue area. For more information refer to Store Queues in the manual. SH3 and SH2A: Reads a 16-byte data block into the cache. The address specified by Rn should be on 32-bit boundary. No address related error is detected in this instruction. In case of an error, the instruction operates as NOP. Note: On products with no cache, this instruction is handled as a NOP instruction.","void PREF (int n) {
 prefetch_operand_cache_block (R[n]);
 PC += 2;
}"
prefi @Rn,0000nnnn11010011,Reads 32-byte instruction block into instruction cache,"Reads a 32-byte block of data starting at a 32-byte boundary within the instruction cache. The lower 5 bits of the address specified by Rn are masked by zeroes. This instruction does not generate data address error and MMU exceptions. In the event of an error, the PREFI instruction is treated as an NOP (no operation) instruction. When the address to be prefetched is missing from UTLB or is protected, the PREFI instruction is treated as an NOP instruction and a TLB exception does not occur. Note: This instruction can be used before the SLEEP command is issued to prefetch instructions for execution on return from the SLEEP state.","void PREFI (int n) {
 prefetch_instruction_cache_block (R[n]);
 PC += 2;
}"
resbank,0000000001011011,"Bank -> R0 to R14, GBR, MACH, MACL, PR",Restores the last register saved to a register bank. Note: The issue cycle count is 19 when a bank overflow has occured and the registers are restored from the stack.,"void RESBANK (void) {
 int m; // Number of register bank to which a save was last performed.
 if (BO == 0)
 {
 PR = Register_Bank[m].PR_BANK;
 GBR = Register_Bank[m].GBR_BANK;
 MACL = Register_Bank[m].MACL_BANK;
 MACH = Register_Bank[m].MACH_BANK;
 for (int i = 0; i <= 14; i++)
 R[i] = Register_Bank[m].R_BANK[i];
 }
 else
 {
 for (int i = 0; i <= 14; i++)
 {
 R[i] = Read_32 (R[15]);
 R[15] += 4;
 }
 PR = Read_32 (R[15]);
 R[15] += 4;
 GBR = Read_32 (R[15]);
 R[15] += 4;
 MACH = Read_32 (R[15]);
 R[15] += 4;
 MACL = Read_32 (R[15]);
 R[15] += 4;
 }
 PC += 2;
}"
"pcopy Sx,Dz",111110********** 11011001xx00zzzz,Sx -> Dz,"Stores the Sx operand in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits are also updated.","void pcopy_sx (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_SRC2 = 0;
 DSP_ALU_SRC2G = 0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_plus_dc_bit.c""
}"
"pand Sx,Sy,Dz",111110********** 10010101xxyyzzzz,"Sx & Sy -> Dz, clear LSW of Dz","Does an AND of the upper word of the Sx operand and the upper word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pand (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW & DSP_ALU_SRC2_HW;
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 A0G = 0x0; // clear Guard bits
 else if (ex2_dz_no == 1)
 A1G = 0x0;
 carry_bit = 0x0;
 negative_bit = DSP_ALU_DST_MSB;
 zero_bit = (DSP_ALU_DST_HW == 0);
 overflow_bit = 0x0;
 #include ""logical_dc_bit.c""
}"
"pand Sx,Sy,Dz",111110********** 10010101xxyyzzzz,"Sx & Sy -> Dz, clear LSW of Dz","Does an AND of the upper word of the Sx operand and the upper word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pand (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW & DSP_ALU_SRC2_HW;
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 A0G = 0x0; // clear Guard bits
 else if (ex2_dz_no == 1)
 A1G = 0x0;
 carry_bit = 0x0;
 negative_bit = DSP_ALU_DST_MSB;
 zero_bit = (DSP_ALU_DST_HW == 0);
 overflow_bit = 0x0;
 #include ""logical_dc_bit.c""
}"
fschg,1111001111111101,"If FPSCR.PR = 0: ~FPSCR.SZ -> FPSCR.SZ
Else: Undefined Operation","Inverts the SZ bit of the floating-point status register FPSCR. Changing the value of the SZ bit in FPSCR switches the amount of data for transfer by the FMOV instruction between one single-precision data and a pair of single-precision data. When FPSCR.SZ = 0, an FMOV instruction transfers a single-precision number. When FPSCR.SZ = 1, the FMOV instruction transfers a pair of single-precision numbers.","void FSCHG (void)
{
 if (FPSCR_PR == 0)
 {
 FPSCR ^= 0x00100000; // toggle bit 20
 PC += 2;
 }
 else
 undefined_operation ();
}"
fpchg,1111011111111101,~FPSCR.PR -> FPSCR.PR,Inverts the PR bit of the floating-point status register FPSCR. The value of this bit selects single-precision or double-precision operation.,"void FPCHG (void)
{
 FPSCR ^= 0x00080000; // toggle bit 19
 PC += 2;
}"
"fmul DRm,DRn",1111nnn0mmm00010,DRn * DRm -> DRn,"Arithmetically multiplies the two double-precision floating-point numbers in DRn and DRm, and stores the result in FRn.","void FMUL (int m, int n) {
 PC += 2;
 clear_cause ();
 if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
 invalid (n);
 else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
 qnan (n);
 else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
 set_E ();
 else
 switch (data_type_of (m))
 {
 case NORM:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 zero (n, sign_of (m) ^ sign_of (n));
 break;
 case PINF:
 case NINF:
 inf (n, sign_of (m) ^ sign_of (n));
 break;
 default:
 normal_fmul (m, n);
 break;
 }
 break;
 case PZERO:
 case NZERO:
 switch (data_type_of (n))
 {
 case PINF:
 case NINF:
 invalid (n);
 break;
 default:
zero (n,sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 case PINF:
 case NINF:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 invalid (n);
 break;
 default:
 inf (n, sign_of (m) ^ sign_of (n));
 break
 }
 break;
 }
}"
"fmov.d XDm,@Rn",1111nnnnmmm11010,XDm -> (Rn),Transfers contents of memory at address indicated by (R0 + Rm) to XDn.,"void FMOV_STORE_XD (int m, int n) {
 Write_64 (R[n], XD[m >> 1]);
 PC += 2;
}"
"fmov.d @Rm+,DRn",1111nnn0mmmm1001,"(Rm) -> DRn, Rm + 8 -> Rm","Transfers contents of memory at address indicated by Rm to DRn, and adds 8 to Rm.","void FMOV_RESTORE_DR (int m, int n) {
 DR[n >> 1] = Read_64 (R[m]);
 R[m] += 8;
 PC += 2;
}"
"fmov.d @Rm+,XDn",1111nnn1mmmm1001,"(Rm) -> XDn, Rm+8 -> Rm","Transfers contents of memory at address indicated by Rm to XDn, and adds 8 to Rm.","void FMOV_RESTORE_XD (int m, int n) {
 XD[n >> 1] = Read_64 (R[m]);
 R[m] += 8;
 PC += 2;
}"
"fmov.d DRm,@-Rn",1111nnnnmmm01011,"Rn-8 -> Rn, DRm -> (Rn)","Subtracts 8 from Rn, and transfers DRm contents to memory at address indicated by resulting Rn value.","void FMOV_SAVE_DR (int m, int n) {
 Write_64 (R[n] - 8, DR[m >> 1]);
 R[n] -= 8;
 PC += 2;
}"
"fmov.d XDm,@-Rn",1111nnnnmmm11011,"Rn-8 -> Rn, (Rn) -> XDm","Subtracts 8 from Rn, and transfers XDm contents to memory at address indicated by resulting Rn value.","void FMOV_SAVE_XD (int m, int n) {
 Write_64 (R[n] - 8, XD[m >> 1]);
 R[n] -= 8;
 PC += 2;
}"
"fmov.d @(R0,Rm),DRn",1111nnn0mmmm0110,(R0 + Rm) -> DRn,Transfers contents of memory at address indicated by (R0 + Rm) to DRn.,"void FMOV_INDEX_LOAD_DR (int m, int n) {
 DR[n >> 1] = Read_64 (R[0] + R[m]);
 PC += 2;
}"
"fmov.d @(R0,Rm),XDn",1111nnn1mmmm0110,(R0 + Rm) -> XDn,Transfers contents of memory at address indicated by (R0 + Rm) to XDn.,"void FMOV_INDEX_LOAD_XD (int m, int n) {
 XD[n >> 1] = Read_64 (R[0] + R[m]);
 PC += 2;
}"
"lds Rm,FPUL",0100mmmm01011010,Rm -> FPUL,Loads the source operand into FPU system register FPUL.,"void LDSFPUL (int m) {
 FPUL = R[m];
 PC += 2;
}"
"sts FPUL,Rn",0000nnnn01011010,FPUL -> Rn,Stores FPU system register FPUL in the destination.,"void STSFPUL (int n) {
 R[n] = FPUL;
 PC += 2;
}"
"lds.l @Rm+,FPUL",0100mmmm01010110,"(Rm) -> FPUL, Rm+4 -> Rm",,"void LDSMFPUL (int m) {
 FPUL = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"sts.l FPUL,@-Rn",0100nnnn01010010,"Rn-4 -> Rn, FPUL -> (Rn)",Stores FPU system register FPUL in the destination.,"void STSMFPUL (int n) {
 R[n] -= 4;
 Write_32 (R[n], FPUL);
 PC += 2;
}"
frchg,1111101111111101,"If FPSCR.PR = 0: ~FPSCR.FR -> FPSCR.FR
Else: Undefined Operation",Inverts the FR bit in floating-point register FPSCR.,"void FRCHG (void) {
 if (FPSCR_PR == 0)
 {
 FPSCR ^= 0x00200000; // toggle bit 21
 PC += 2;
 }
 else
 undefined_operation ();
}"
"dcf pcopy Sy,Dz",111110********** 1111101100yyzzzz,If DC = 0: Sy -> Dz Else: nop,"Conditionally stores the Sy operand in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pcopy_sy_dcf (void) {
 DSP_ALU_SRC1 = 0;
 DSP_ALU_SRC1G = 0;
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"mov.b @Rm,Rn",0110nnnnmmmm0000,(Rm) -> sign extension -> Rn,Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.,"void MOVBL (int m, int n) {
 R[n] = Read_8 (R[m]);
 if ((R[n] & 0x80) == 0)
 R[n] &= 0x000000FF;
 else
 R[n] |= 0xFFFFFF00;
 PC += 2;
}"
"mov.w @Rm,Rn",0110nnnnmmmm0001,(Rm) -> sign extension -> Rn,Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.,"void MOVWL (int m, int n) {
 R[n] = Read_16 (R[m]);
 if ((R[n] & 0x8000) == 0)
 R[n] &= 0x0000FFFF;
 else
 R[n] |= 0xFFFF0000;
 PC += 2;
}"
"mov.l @Rm,Rn",0110nnnnmmmm0010,(Rm) -> Rn,Transfers the source operand to the destination.,"void MOVLL (int m, int n) {
 R[n] = Read_32 (R[m]);
 PC += 2;
}"
"mov.b Rm,@Rn",0010nnnnmmmm0000,Rm -> (Rn),Transfers the source operand to the destination.,"void MOVBS (int m, int n) {
 Write_8 (R[n], R[m]);
 PC += 2;
}"
"mov.w Rm,@Rn",0010nnnnmmmm0001,Rm -> (Rn),Transfers the source operand to the destination.,"void MOVWS (int m, int n) {
 Write_16 (R[n], R[m]);
 PC += 2;
}"
"mov.l Rm,@Rn",0010nnnnmmmm0010,Rm -> (Rn),Transfers the source operand to the destination.,"void MOVLS (int m, int n) {
 Write_32 (R[n], R[m]);
 PC += 2;
}"
"mov.b @Rm+,Rn",0110nnnnmmmm0100,"(Rm) -> sign extension -> Rn, Rm+1 -> Rm",Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.,"void MOVBP (int m, int n) {
 R[n] = Read_8 (R[m]);
 if ((R[n] & 0x80) == 0)
 R[n] &= 0x000000FF;
 else
 R[n] |= 0xFFFFFF00;
 if (n != m)
 R[m] += 1;
 PC += 2;
}"
"ldc.l @Rm+,VBR",0100mmmm00100111,"(Rm) -> VBR, Rm+4 -> Rm",Stores a source operand in control register VBR.,"void LDCMVBR (int m) {
 VBR = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"ldc Rm,MOD",0100mmmm01011110,Rm -> MOD,Stores a source operand in control register MOD.,"void LDCMOD (int m) {
 MOD = R[m];
 PC += 2;
}"
"ldc.l @Rm+,MOD",0100mmmm01010111,"(Rm) -> MOD, Rm+4 -> Rm",Stores a source operand in control register MOD.,"void LDCMMOD (int m) {
 MOD = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"ldc Rm,RE",0100mmmm01111110,Rm -> RE,Stores a source operand in control register RE.,"void LDCRE (int m) {
 RE = R[m];
 PC += 2;
}"
"ldc.l @Rm+,RE",0100mmmm01110111,"(Rm) -> RE, Rm+4 -> Rm",Stores a source operand in control register RE.,"void LDCMRE (int m) {
 RE = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"ldc Rm,RS",0100mmmm01101110,Rm -> RS,Stores a source operand in control register RS.,"void LDCRS (int m) {
 RS = R[m];
 PC += 2;
}"
"ldc.l @Rm+,RS",0100mmmm01100111,"(Rm) -> RS, Rm+4 -> Rm",Stores a source operand in control register RS.,"void LDCMRS (int m) {
 RS = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"dct psub Sx,Sy,Dz",111110********** 10100010xxyyzzzz,If DC = 1: Sx - Sy -> Dz Else: nop,"Conditionally subtracts the contents of the Sy operand from the Sx operand and stores the result in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void psub_dct (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"fcnvsd FPUL,DRn",1111nnn010101101,float_to_double (FPUL) -> DRn,"Converts the single-precision floating-point number in FPUL to a double-precision floating-point number, and stores the result in DRn.","void FCNVSD (int n) {
 if (FPSCR_PR != 1)
 undefined_operation ();
 else
 {
 switch (fpul_type ())
 {
 case PZERO:
 case NZERO:
 case PINF:
 case NINF:
 case NORM:
 DR[n >> 1] = FPUL; // convert float to double
 break;
 case DENORM:
 set_E ();
 break;
 case qNaN:
 qnan (n);
 break;
 case sNaN:
 invalid (n);
 break;
 }
 }
}"
"dct pdec Sy,Dz",111110********** 1010101000yyzzzz,"If DC = 1: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop","Conditionally subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pdec_sy_dct (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"bld #imm3,Rn",10000111nnnn1iii,imm of Rn -> T,Stores a specified bit of the LSB 8 bits of a general register Rn in the T bit. The bit number is specified by 3-bit immediate data.,"void BLD (int i, int n) {
 long imm, assignbit;
 imm = (0x00000007 & (long)i);
 assignbit = (0x00000001 << imm) & R[n];
 if (assignbit == 0)
 T = 0;
 else
 T = 1;
 PC += 2;
}"
"bldnot.b #imm3,@(disp12,Rn)",0011nnnn0iii1001 1011dddddddddddd,~(imm of (disp+Rn)) -> T,"Inverts a specified bit of memory at the address indicated by (disp + Rn), and stores the resulting value in the T bit. The bit number is specified by 3-bit immediate data. Data is read from memory as a byte unit.","void BLDNOTM (int d, int i, int n) {
 long disp = (0x00000FFF & (long)d);
 long imm = (0x00000007 & (long)i);
 long temp = Read_8 (R[n] + disp);
 long assignbit = (0x00000001 << imm) & temp;
 if (assignbit == 0)
 T = 1;
 else
 T = 0;
 PC += 4;
}"
pclr Dz,111110********** 100011010000zzzz,0x00000000 -> Dz,"Clears the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The Z bit of the DSR register is set to 1. The N, V, and GT bits are cleared to 0.","void pclr (void) {
 DSP_REG[ex2_dz_no] = 0x0;
 if (ex2_dz_no == 0)
 A0G = 0x0;
 else if (ex2_dz_no == 1)
 A1G = 0x0;
 carry_bit = 0;
 negative_bit = 0;
 zero_bit = 1;
 overflow_bit = 0;
 #include ""fixed_pt_plus_dc_bit.c""
}"
"sts.l Y0,@-Rn",0100nnnn10100010,"Rn-4 -> Rn, Y0 -> (Rn)",Stores DSP register Y0 in the destination.,"void STSMY0 (int n) {
 R[n] -= 4;
 Write_32 (R[n], Y0);
 PC += 2;
}"
"sts Y1,Rn",0000nnnn10111010,Y1 -> Rn,Stores DSP register Y1 in the destination.,"void STSY1 (int n) {
 R[n] = Y1;
 PC += 2;
}"
"sts.l Y1,@-Rn",0100nnnn10110010,"Rn-4 -> Rn, Y1 -> (Rn)",Stores DSP register Y1 in the destination.,"void STSMY1 (int n) {
 R[n] -= 4;
 Write_32 (R[n], Y1);
 PC += 2;
}"
synco,0000000010101011,Prevents the next instruction from being issued until instructions issued before this instruction has been completed.,"This instruction is used to synchronize data operations. When this instruction is executed, the subsequent bus accesses are not executed until the execution of all preceding bus accesses has been completed.","void SYNCO (void) {
 synchronize_data_operaiton ();
 PC += 2;
}"
trapa #imm,11000011iiiiiiii,"SH1*,SH2*: PC/SR -> stack area, (imm*4 + VBR) -> PC
SH3*,SH4*: PC/SR -> SPC/SSR, imm*4 -> TRA, 0x160 -> EXPEVT, VBR + 0x0100 -> PC",Starts trap exception handling.,"void TRAPA (int i) {
 int imm = (0x000000FF & i);
 #if SH1 || SH2 || SH2A
 R[15] -= 4;
 Write_32 (R[15], SR);
 R[15] -= 4;
 Write_32 (R[15], PC + 2);
 PC = Read_32 (VBR + (imm << 2));
 #elif SH3 || SH4 || SH4A
 TRA = imm << 2;
 SSR = SR;
 SPC = PC + 2;
 SGR = R15;
 SR.MD = 1;
 SR.BL = 1;
 SR.RB = 1;
 EXPEVT = 0x00000160;
 PC = VBR + 0x00000100;
 #endif
}"
"fmov FRm,FRn",1111nnnnmmmm1100,FRm -> FRn,Transfers FRm contents to FRn.,"void FMOV (int m, int n) {
 FR[n] = FR[m];
 PC += 2;
}"
"fmov.s @Rm,FRn",1111nnnnmmmm1000,(Rm) -> FRn,Transfers contents of memory at address indicated by Rm to FRn.,"void FMOV_LOAD (int m, int n) {
 FR[n] = Read_32 (R[m]);
 PC += 2;
}"
"mov.w R0,@(disp,Rn)",10000001nnnndddd,R0 -> (disp*2 + Rn),"Transfers the source operand to the destination. The 4-bit displacement is multiplied by two after zero-extension, enabling a range up to +30 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead.","void MOVWS4 (int d, int n) {
 long disp = (0x0000000F & (long)d);
 Write_16 (R[n] + (disp << 1), R[0]);
 PC += 2;
}"
"mov.w Rm,@(disp12,Rn)",0011nnnnmmmm0001 0001dddddddddddd,Rm -> (disp*2 + Rn),Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack.,"void MOVWS12 (int d, int m, int n) {
 long disp = (0x00000FFF & (long)d);
 Write_16 (R[n] + (disp << 1), R[m]);
 PC += 4;
}"
"mov.l Rm,@(disp,Rn)",0001nnnnmmmmdddd,Rm -> (disp*4 + Rn),"Transfers the source operand to the destination. The 4-bit displacement is multiplied by four after zero-extension, enabling a range up to +60 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead.","void MOVLS4 (int m, int d, int n) {
 long disp = (0x0000000F & (long)d);
 Write_32 (R[n] + (disp << 2), R[m]);
 PC += 2;
}"
"mov.l Rm,@(disp12,Rn)",0011nnnnmmmm0001 0010dddddddddddd,Rm -> (disp*4 + Rn),Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack.,"void MOVLS12 (int d, int m, int n) {
 long disp = (0x00000FFF & (long)d);
 Write_32 (R[n] + (disp << 2), R[m]);
 PC += 4;
}"
"mov.b @(R0,Rm),Rn",0000nnnnmmmm1100,(R0 + Rm) -> sign extension -> Rn,Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.,"void MOVBL0 (int m, int n) {
 R[n] = Read_8 (R[m] + R[0]);
 if ((R[n] & 0x80) == 0)
 R[n] &= 0x000000FF;
 else R[n] |= 0xFFFFFF00;
 PC += 2;
}"
"mov.w @(R0,Rm),Rn",0000nnnnmmmm1101,(R0 + Rm) -> sign extension -> Rn,Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.,"void MOVWL0 (int m, int n) {
 R[n] = Read_16 (R[m] + R[0]);
 if ((R[n] & 0x8000) == 0)
 R[n] &= 0x0000FFFF;
 else
 R[n] |= 0xFFFF0000;
 PC += 2;
}"
"mov.l @(R0,Rm),Rn",0000nnnnmmmm1110,(R0 + Rm) -> Rn,Transfers the source operand to the destination.,"void MOVLL0 (int m, int n) {
 R[n] = Read_32 (R[m] + R[0]);
 PC += 2;
}"
"movs.l Ds,@As+Is",111101AADDDD1111,"Ds -> (As), As+Is -> As",Transfers the source operand data to the destination. The transferred data is a longword.,
"pabs Sx,Dz",111110********** 10001000xx00zzzz,"If Sx >= 0: Sx -> Dz
If Sx < 0: 0 - Sx -> Dz","Finds absolute values. When the Sx operand is positive, the contents of the operand are transferred to the Dz operand. If the value is negative, the value of the Sx operand is subtracted from 0 and stored in the Dz operand.",
"pabs Sy,Dz",111110********** 1010100000yyzzzz,"If Sy >= 0: Sy -> Dz
If Sy < 0: 0 - Sy -> Dz","Finds absolute values. When the Sy operand is positive, the contents of the operand are transferred to the Dz operand. If the value is negative, the value of the Sy operand is subtracted from 0 and stored in the Dz operand.",
"padd Sx,Sy,Dz",111110********** 10110001xxyyzzzz,Sx + Sy -> Dz,Adds the contents of the Sx and Sy operands and stores the result in the Dz operand.,
"dct padd Sx,Sy,Dz",111110********** 10110010xxyyzzzz,"If DC = 1: Sx + Sy -> Dz
Else: nop","Conditionally adds the contents of the Sx and Sy operands and stores the result in the Dz operand. The instruction is executed if the DC bit is set to 1. Otherwise, no operation is performed.",
"dcf padd Sx,Sy,Dz",111110********** 10110011xxyyzzzz,"If DC = 0: Sx + Sy -> Dz
Else: nop","Conditionally adds the contents of the Sx and Sy operands and stores the result in the Dz operand. The instruction is executed if the DC bit is set to 0. Otherwise, no operation is performed.",
"padd Sx,Sy,Du
pmuls Se,Sf,Dg",111110********** 0111eeffxxyygguu,"Sx + Sy -> Du
MSW of Se * MSW of Sf -> Dg",Adds the contents of the Sx and Sy operands and stores the result in the Du operand. The contents of the top word of the Se and Sf operands are multiplied as signed and the result stored in the Dg operand. These two processes are executed simultaneously in parallel.,
"paddc Sx,Sy,Dz",111110********** 10110000xxyyzzzz,Sx + Sy + DC -> Dz,"Adds the contents of the Sx and Sy operands to the DC bit and stores the result in the Dz operand. The DC bit of the DSR register is updated as the carry flag. The N, Z, V, and GT bits of the DSR register are also updated.","void paddc (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2 + DSPDCBIT;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_dc_always_carry.c""
}"
"fcmp/gt DRm,DRn",1111nnn0mmm00101,If DRn > DRm: 1 -> T Else: 0 -> T,"Arithmetically compares the two double-precision floating-point numbers in DRn and DRm, and stores 1 in the T bit if DRn > DRm, or 0 otherwise.","void FCMP_GT (int m, int n) {
 PC += 2;
 clear_cause ();
 if (fcmp_chk_double (m, n) == INVALID || fcmp_chk_double (m, n) == UO)
 fcmp_invalid ();
 else if (fcmp_chk_double (m, n) == GT)
 T = 1;
 else
 T = 0;
}
int fcmp_chk_double (int m, int n) {
 // see description of FCMP/EQ instruction.
}
void fcmp_invalid (void) {
 // see description of FCMP/EQ instruction.
}"
"mov.b Rm,@(R0,Rn)",0000nnnnmmmm0100,Rm -> (R0 + Rn),Transfers the source operand to the destination.,"void MOVBS0 (int m, int n) {
 Write_8 (R[n] + R[0], R[m]);
 PC += 2;
}"
"mov.w Rm,@(R0,Rn)",0000nnnnmmmm0101,Rm -> (R0 + Rn),Transfers the source operand to the destination.,"void MOVWS0 (int m, int n) {
 Write_16 (R[n] + R[0], R[m]);
 PC += 2;
}"
"mov.l Rm,@(R0,Rn)",0000nnnnmmmm0110,Rm -> (R0 + Rn),Transfers the source operand to the destination.,"void MOVLS0 (int m, int n) {
 Write_32 (R[n] + R[0], R[m]);
 PC += 2;
}"
"mov.b @(disp,GBR),R0",11000100dddddddd,(disp + GBR) -> sign extension -> R0,"Transfers the source operand to the destination. The 8-bit displacement is only zero-extended, so a range up to +255 bytes can be specified. The loaded data is sign-extended to 32 bit before being stored in the destination register.","void MOVBLG (int d) {
 unsigned int disp = (0x000000FF & d);
 R[0] = Read_8 (GBR + disp);
 if ((R[0] & 0x80) == 0)
 R[0] &= 0x000000FF;
 else
 R[0] |= 0xFFFFFF00;
 PC += 2;
}"
"mov.w @(disp,GBR),R0",11000101dddddddd,(disp*2 + GBR) -> sign extension -> R0,"Transfers the source operand to the destination. The 8-bit displacement is multiplied by two after zero-extension, enabling a range up to +510 bytes to be specified. The loaded data is sign-extended to 32 bit before being stored in the destination register.","void MOVWLG (int d) {
 unsigned int disp = (0x000000FF & d);
 R[0] = Read_16 (GBR + (disp << 1));
 if ((R[0] & 0x8000) == 0)
 R[0] &= 0x0000FFFF;
 else
 R[0] |= 0xFFFF0000;
 PC += 2;
}"
"mov.l @(disp,GBR),R0",11000110dddddddd,(disp*4 + GBR) -> R0,"Transfers the source operand to the destination. The 8-bit displacement is multiplied by four after zero-extension, enabling a range up to +1020 bytes to be specified.","void MOVLLG (int d) {
 unsigned int disp = (0x000000FF & d);
 R[0] = Read_32 (GBR + (disp << 2));
 PC += 2;
}"
"mov.b R0,@(disp,GBR)",11000000dddddddd,R0 -> (disp + GBR),"Transfers the source operand to the destination. The 8-bit displacement is only zero-extended, so a range up to +255 bytes can be specified.","void MOVBSG (int d) {
 unsigned int disp = (0x000000FF & d);
 Write_8 (GBR + disp, R[0]);
 PC += 2;
}"
"pinc Sx,Dz",111110********** 10011001xx00zzzz,"MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz","Adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pinc_sx (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 #include ""integer_unconditional_update.c""
 #include ""integer_plus_dc_bit.c""
}"
"mov.w @Rm+,Rn",0110nnnnmmmm0101,"(Rm) -> sign extension -> Rn, Rm+2 -> Rm",Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.,"void MOVWP (int m, int n) { R[n] = Read_16 (R[m]); if ((R[n] & 0x8000) == 0) R[n] &= 0x0000FFFF; else R[n] |= 0xFFFF0000; if (n != m) R[m] += 2; PC += 2; }"
"mov.l @Rm+,Rn",0110nnnnmmmm0110,"(Rm) -> Rn, Rm+4 -> Rm",Transfers the source operand to the destination.,"void MOVLP (int m, int n) { R[n] = Read_32 (R[m]); if (n != m) R[m] += 4; PC += 2; }"
"mov.b Rm,@-Rn",0010nnnnmmmm0100,"Rn-1 -> Rn, Rm -> (Rn)",Transfers the source operand to the destination.,"void MOVBM (int m, int n) { Write_8 (R[n] - 1, R[m]); R[n] -= 1; PC += 2; }"
"mov.w Rm,@-Rn",0010nnnnmmmm0101,"Rn-2 -> Rn, Rm -> (Rn)",Transfers the source operand to the destination.,"void MOVWM (int m, int n) { Write_16 (R[n] - 2, R[m]); R[n] -= 2; PC += 2; }"
"mov.l Rm,@-Rn",0010nnnnmmmm0110,"Rn-4 -> Rn, Rm -> (Rn)",Transfers the source operand to the destination.,"void MOVLM (int m, int n) { Write_32 (R[n] - 4, R[m]); R[n] -= 4; PC += 2; }"
"mov.b @-Rm,R0",0100mmmm11001011,"Rm-1 -> Rm, (Rm) -> sign extension -> R0",Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.,void MOVRSBM (int m) { R[m] -= 1; R[0] = Read_16 (R[m]); if ((R[0] & 0x80) == 0) R[0] &= 0x000000FF; else R[0] |= 0xFFFFFF00; PC+=2; }
"mov.w @-Rm,R0",0100mmmm11011011,"Rm-2 -> Rm, (Rm) -> sign extension -> R0",Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.,void MOVRSWM (int m) { R[m]-= 2; R[0] = Read_16 (R[m]); if ((R[0] & 0x8000) == 0) R[0] &= 0x0000FFFF; else R[0] |= 0xFFFF0000; PC += 2; }
"dct pinc Sy,Dz",111110********** 1011101000yyzzzz,"If DC = 1: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pinc_sy_dct (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"fsts FPUL,FRn",1111nnnn00001101,FPUL -> FRn,Transfers the contents of system register FPUL to floating-point register FRn.,"void FSTS (int n) {
 FR[n] = FPUL;
 PC += 2;
}"
fabs FRn,1111nnnn01011101,FRn & 0x7FFFFFFF -> FRn,"Clears the most significant bit of the contents of floating-point register FRn to 0, and stores the result in FRn.","void FABS (int n) {
 FR[n] = FR[n] & 0x7FFFFFFFF;
 PC += 2;
}"
fneg FRn,1111nnnn01001101,FRn ^ 0x80000000 -> FRn,"Inverts the most significant bit (sign bit) of the contents of floating-point register FRn, and stores the result in FRn.","void FNEG (int n) {
 FR[n] = -FR[n];
 PC += 2;
}"
"fcnvds DRm,FPUL",1111mmm010111101,double_to_float (DRm) -> FPUL,"Converts the double-precision floating-point number in DRm to a single-precision floating-point number, and stores the result in FPUL.","void FCNVDS (int m) {
 if (FPSCR_PR != 1)
 undefined_operation ();
 else
 {
 PC += 2;
 clear_cause ();
 switch (data_type_of (m))
 {
 case NORM:
 case PZERO:
 case NZERO:
 normal_fcnvds (m, &FPUL);
 break;
 case DENORM:
 set_E ();
 case PINF:
 FPUL = 0x7F800000;
 break;
 case NINF:
 FPUL = 0xFF800000;
 break;
 case qNaN:
 FPUL = 0x7FBFFFFF;
 break;
 case sNaN:
 set_V ();
 if ((FPSCR & ENABLE_V) == 0)
 FPUL = 0x7FBFFFFF;
 else
 fpu_exception_trap ();
 break;
 }
 }
}"
"dct pcopy Sx,Dz",111110********** 11011010xx00zzzz,If DC = 1: Sx -> Dz Else: nop,"Conditionally stores the Sx operand in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pcopy_sx_dct (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_SRC2 = 0;
 DSP_ALU_SRC2G = 0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"swap.w Rm,Rn",0110nnnnmmmm1001,Rm -> swap upper/lower words -> Rn,Swaps the upper and lower parts of the contents of general register Rm and stores the result in Rn. The 16 bits from bit 31 to bit 16 of Rm are swapped with the 16 bits from bit 15 to bit 0.,"void SWAPW (int m, int n) {
 unsigned long temp;
 temp = (R[m] >> 16) & 0x0000FFFF;
 R[n] = R[m] << 16;
 R[n] |= temp;
 PC += 2;
}"
"xtrct Rm,Rn",0010nnnnmmmm1101,Rm:Rn middle 32 bits -> Rn,"Extracts the middle 32 bits from the 64-bit contents of linked general registers Rm and Rn, and stores the result in Rn.","void XTRCT (int m, int n) {
 unsigned long high = (R[m] << 16) & 0xFFFF0000;
 unsigned long low = (R[n] >> 16) & 0x0000FFFF;
 R[n] = high | low;
 PC += 2;
}"
"psub Sx,Sy,Du
pmuls Se,Sf,Dg",111110********** 0110eeffxxyygguu,"Sx - Sy -> Du
MSW of Se * MSW of Sf -> Dg","Subtracts the contents of the Sy operand from the Sx operand and stores the result in the Du operand. The contents of the top word of the Se and Sf operands are multiplied as signed and the result stored in the Dg operand. These two processes are executed simultaneously in parallel.
The DC bit of the DSR register is updated according to the results of the ALU operation and the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated according to the results of the ALU operation.","void psub_pmuls (void)
{
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 switch (EX2_DU)
 {
 case 0x0:
 X0 = DSP_ALU_DST;
 negative_bit = DSP_ALU_DST_MSB;
 zero_bit = (DSP_ALU_DST == 0);
 break;
 case 0x1:
 Y0 = DSP_ALU_DST;
 negative_bit = DSP_ALU_DST_MSB;
 zero_bit = (DSP_ALU_DST == 0);
 break;
 case 0x2:
 A0 = DSP_ALU_DST;
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 negative_bit = DSP_ALU_DSTG_BIT7;
 zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
 break;
 case 0x3:
 A1 = DSP_ALU_DST;
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 negative_bit = DSP_ALU_DSTG_BIT7;
 zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
 break;
 }
 #include ""fixed_pt_minus_dc_bit.c""
}"
"cmp/str Rm,Rn",0010nnnnmmmm1100,If Rn and Rm have an equal byte: 1 -> T Else: 0 -> T,"Compares general registers Rn and Rm, and sets the T bit if any of the 4 bytes in Rn are equal to the corresponding byte in Rm. The contents of Rn and Rm are not changed.","void CMPSTR (int m, int n) { unsigned long temp; long HH, HL, LH, LL; temp = R[n] ^ R[m]; HH = (temp & 0xFF000000) >> 24; HL = (temp & 0x00FF0000) >> 16; LH = (temp & 0x0000FF00) >> 8; LL = temp & 0x000000FF; HH = HH && HL && LH && LL; if (HH == 0) T = 1; else T = 0; PC += 2; }"
clips.b Rn,0100nnnn10010001,"If Rn > 0x0000007F: 0x0000007F -> Rn, 1 -> CS If Rn < 0xFFFFFF80: 0xFFFFFF80 -> Rn, 1 -> CS","Determines saturation. Signed data is used with this instruction. The saturation upper-limit value is stored in general register Rn if the contents of Rn exceed the saturation upper-limit value, or the saturation lower-limit value is stored in Rn if the contents of Rn are less than the saturation lower-limit value, and the CS bit is set to 1. The saturation upper-limit value is 0x0000007F (127). The saturation lower-limit value is 0xFFFFFF80 (-128).",void CLIPSB (int n) { if (R[n] > 0x0000007F) { R[n] = 0x0000007F; CS = 1; } else if (R[n] < 0xFFFFFF80) { R[n] = 0xFFFFFF80; CS = 1; } PC += 2; }
clips.w Rn,0100nnnn10010101,"If Rn > 0x00007FFF: 0x00007FFF -> Rn, 1 -> CS If Rn < 0xFFFF8000: 0xFFFF8000 -> Rn, 1 -> CS","Determines saturation. Signed data is used with this instruction. The saturation upper-limit value is stored in general register Rn if the contents of Rn exceed the saturation upper-limit value, or the saturation lower-limit value is stored in Rn if the contents of Rn are less than the saturation lower-limit value, and the CS bit is set to 1. The saturation upper-limit value is 0x00007FFF (32767). The saturation lower-limit value is 0xFFFF8000 (-32768).",void CLIPSW (int n) { if (R[n] > 0x00007FFF) { R[n] = 0x00007FFF; CS = 1; } else if (R[n] < 0xFFFF8000) { R[n] = 0xFFFF8000; CS = 1; } PC += 2; }
clipu.b Rn,0100nnnn10000001,"If Rn > 0x000000FF: 0x000000FF -> Rn, 1 -> CS","Determines saturation. Unsigned data is used with this instruction. If the contents of general register Rn exceed the saturation value, the saturation value is stored in Rn and the CS bit is set to 1. The saturation value is 0x000000FF (255).",void CLIPUB (int n) { if (R[n] > 0x000000FF) { R[n] = 0x000000FF; CS = 1; } PC += 2; }
clipu.w Rn,0100nnnn10000101,"If Rn > 0x0000FFFF: 0x0000FFFF -> Rn, 1 -> CS","Determines saturation. Unsigned data is used with this instruction. If the contents of general register Rn exceed the saturation value, the saturation value is stored in Rn and the CS bit is set to 1. The saturation value is 0x0000FFFF (65535).",void CLIPUW (int n) { if (R[n] > 0x0000FFFF) { R[n] = 0x0000FFFF; CS = 1; } PC += 2; }
"div0s Rm,Rn",0010nnnnmmmm0111,"MSB of Rn -> Q, MSB of Rm -> M, M ^ Q -> T","Performs initial settings for signed division. This instruction is followed by a DIV1 instruction that executes 1-digit division, for example, and repeated division steps are executed to find the quotient. See the description of the DIV1 instruction for details.","void DIV0S (int m, int n) { if ((R[n] & 0x80000000) == 0) Q = 0; else Q = 1; if ((R[m] & 0x80000000) == 0) M = 0; else M = 1; T = ! (M == Q); PC += 2; }"
div0u,0000000000011001,"0 -> M, 0 -> Q, 0 -> T","Performs initial settings for unsigned division. This instruction is followed by a DIV1 instruction that executes 1-digit division, for example, and repeated division steps are executed to find the quotient. See the description of the DIV1 instruction for details.",void DIV0U (void) { M = Q = T = 0; PC += 2; }
"plds Dz,MACH",111110********** 111011010000zzzz,Dz -> MACH,"Stores the Dz operand in the MACH register. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void plds_mach (void) { MACH = DSP_REG[ex2_dz_no]; }
"dcf pinc Sy,Dz",111110********** 1011101100yyzzzz,"If DC = 0: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pinc_sy_dcf (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"dct padd Sx,Sy,Dz",111110********** 10110010xxyyzzzz,If DC = 1: Sx + Sy -> Dz Else: nop,"Conditionally adds the contents of the Sx and Sy operands and stores the result in the Dz operand. The instruction is executed of the DC bit is set to 1. Otherwise no operation is performed. The DC, N, Z, V, and GT bits are not updated.","void padd_dct (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1: DSP_ALU_SRC2 = Y1;
 break;
 case 0x2: DSP_ALU_SRC2 = M0;
 break;
 case 0x3: DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG [ex2_dz_no] = DSP_ALU_DST;
 if(ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7) A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no==1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"movy.w Da,@Ay+Iy",111100*A*D*1**11,"MSW of Da -> (Ay), Ay+Iy -> Ay",Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register.,* of the instruction code is MOVX instruction designation area. MSW = High-order word of operand.
"movs.w @-As,Ds",111101AADDDD0000,"As-2 -> As, (As) -> MSW of Ds, 0 -> LSW of Ds","Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.w @As,Ds",111101AADDDD0100,"(As) -> MSW of Ds, 0 -> LSW of Ds","Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.w @As+,Ds",111101AADDDD1000,"(As) -> MSW of Ds, 0 -> LSW of Ds, As+2 -> As","Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.w @As+Ix,Ds",111101AADDDD1100,"(As) -> MSW of Ds, 0 -> LSW of DS, As+Ix -> As","Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"dct pinc Sy,Dz",111110********** 1011101000yyzzzz,"If DC = 1: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pinc_sy_dct (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"dcf pinc Sy,Dz",111110********** 1011101100yyzzzz,"If DC = 0: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pinc_sy_dcf (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"mov.w @(disp,Rm),R0",10000101mmmmdddd,(disp*2 + Rm) -> sign extension -> R0,"Transfers the source operand to the destination. The 4-bit displacement is multiplied by two after zero-extension, enabling a range up to +30 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. The loaded data is sign-extended to 32 bit before being stored in the destination register.","void MOVWL4 (int m, int d) {
 long disp = (0x0000000F & (long)d);
 R[0] = Read_16 (R[m] + (disp << 1));
 if ((R[0] & 0x8000) == 0)
 R[0] &= 0x0000FFFF;
 else
 R[0] |= 0xFFFF0000;
 PC += 2;
}"
"mov.w @(disp12,Rm),Rn",0011nnnnmmmm0001 0101dddddddddddd,(disp*2 + Rm) -> sign extension -> Rn,Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register.,"void MOVWL12 (int d, int m, int n) {
 long disp = (0x00000FFF & (long)d);
 R[n] = Read_16 (R[m] + (disp << 1));
 if ((R[n] & 0x8000) == 0)
 R[n] &= 0x0000FFFF;
 else
 R[n] |= 0xFFFF0000;
 PC += 4;
}"
"dct pneg Sy,Dz",111110********** 1110101000yyzzzz,If DC = 1: 0 - Sy -> Dz Else: nop,"Conditionally reverses the sign. The instruction is executed if the DC bit is set to 1. Subtracts the Sy operand from 0 and stores the result in the Dz operand. The DC, N, Z, V, and GT bits are not updated.","void pneg_sy_dct (void) {
 DSP_ALU_SRC1 = 0;
 DSP_ALU_SRC1G = 0;
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"psub Sx,Sy,Dz",111110********** 10100001xxyyzzzz,Sx - Sy -> Dz,"Subtracts the contents of the Sy operand from the Sx operand and stores the result in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are updated.","void psub (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_minus_dc_bit.c""
}"
"dct pdmsb Sy,Dz",111110********** 1011111000yyzzzz,"If DC = 1: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pdmsb_sy_dct (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"psts MACL,Dz",111110********** 110111010000zzzz,MACL -> Dz,"Stores the contents of the MACL register in the Dz operand. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void psts_macl (void) { DSP_REG[ex2_dz_no] = MACL; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } }
"dct psts MACH,Dz",111110********** 110011100000zzzz,If DC = 1: MACH -> Dz Else: nop,"Conditionally stores the contents of the MACH register in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void psts_mach_dct (void) { if (DC == 1) { DSP_REG[ex2_dz_no] = MACH; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } }
"dct psts MACL,Dz",111110********** 110111100000zzzz,If DC = 1: MACL -> Dz Else: nop,"Conditionally stores the contents of the MACL register in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void psts_macl_dct (void) { if (DC == 1) { DSP_REG[ex2_dz_no] = MACL; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } }
"dcf psts MACH,Dz",111110********** 110011110000zzzz,If DC = 0: MACH -> Dz Else: nop,"Conditionally stores the contents of the MACH register in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void psts_mach_dcf (void) { if (DC == 0) { DSP_REG[ex2_dz_no] = MACH; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } }
"dcf psts MACL,Dz",111110********** 110111110000zzzz,If DC = 0: MACL -> Dz Else: nop,"Conditionally stores the contents of the MACL register in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void psts_macl_dcf (void) { if (DC == 0) { DSP_REG[ex2_dz_no] = MACL; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } }
rotcl Rn,0100nnnn00100100,T << Rn << T,"Rotates the contents of general register Rn one bit to the left through the T bit, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.","void ROTCL (int n) {
 long temp;
 if ((R[n] & 0x80000000) == 0)
 temp = 0;
 else
 temp = 1;
 R[n] <<= 1;
 if (T == 1)
 R[n] |= 0x00000001;
 else
 R[n] &= 0xFFFFFFFE;
 if (temp == 1)
 T = 1;
 else
 T = 0;
 PC += 2;
}"
rotcr Rn,0100nnnn00100101,T >> Rn >> T,"Rotates the contents of general register Rn one bit to the right through the T bit, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.","void ROTCR (int n) {
 long temp;
 if ((R[n] & 0x00000001) == 0)
 temp = 0;
 else
 temp = 1;
 R[n] >>= 1;
 if (T == 1)
 R[n] |= 0x80000000;
 else
 R[n] &= 0x7FFFFFFF;
 if (temp == 1)
 T = 1;
 else
 T = 0;
 PC += 2;
}"
rotl Rn,0100nnnn00000100,T << Rn << MSB,"Rotates the contents of general register Rn one bit to the left, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.","void ROTL (int n) {
 if ((R[n] & 0x80000000) == 0)
 T = 0;
 else
 T = 1;
 R[n] <<= 1;
 if (T == 1)
 R[n] |= 0x00000001;
 else
 R[n] &= 0xFFFFFFFE;
 PC += 2;
}"
rotr Rn,0100nnnn00000101,LSB >> Rn >> T,"Rotates the contents of general register Rn one bit to the right, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.","void ROTR (int n) {
 if ((R[n] & 0x00000001) == 0)
 T = 0;
 else
 T = 1;
 R[n] >>= 1;
 if (T == 1)
 R[n] |= 0x80000000;
 else
 R[n] &= 0x7FFFFFFF;
 PC += 2;
}"
"shad Rm,Rn",0100nnnnmmmm1100,"If Rm >= 0: Rn << Rm -> Rn
If Rm < 0: Rn >> |Rm| -> [MSB -> Rn]",Arithmetically shifts the contents of general register Rn. General register Rm specifies the shift direction and the number of bits to be shifted.,"void SHAD (int m, int n) {
 int sgn = R[m] & 0x80000000;
 if (sgn == 0)
 R[n] <<= (R[m] & 0x1F);
 else if ((R[m] & 0x1F) == 0)
 {
 if ((R[n] & 0x80000000) == 0)
 R[n] = 0;
 else
 R[n] = 0xFFFFFFFF;
 }
 else
 R[n] = (long)R[n] >> ((~R[m] & 0x1F) + 1);
 PC += 2;
}"
shal Rn,0100nnnn00100000,T << Rn << 0,Arithmetically shifts the contents of general register Rn one bit to the left and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.,"void SHAL (int n) {
 if ((R[n] & 0x80000000) == 0)
 T = 0;
 else
 T = 1;
 R[n] <<= 1;
 PC += 2;
}"
shar Rn,0100nnnn00100001,MSB >> Rn >> T,Arithmetically shifts the contents of general register Rn one bit to the right and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.,"void SHAR (int n) {
 long temp;
 if ((R[n] & 0x00000001) == 0)
 T = 0;
 else
 T = 1;
 if ((R[n] & 0x80000000) == 0)
 temp = 0;
 else
 temp = 1;
 R[n] >>= 1;
 if (temp == 1)
 R[n] |= 0x80000000;
 else
 R[n] &= 0x7FFFFFFF;
 PC += 2;
}"
"dcf pdmsb Sx,Dz",111110********** 10011111xx00zzzz,"If DC = 0: Sx data MSB position -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pdmsb_sx_dcf (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"pshl #imm,Dz",111110********** 00010iiiiiiizzzz,"If imm >= 0: Dz << imm -> Dz, clear LSW of Dz
If imm < 0: Dz >> imm, clear LSW of Dz","Logically shifts the top word contents of the Dz operand, stores the result in
the top word of the Dz operand, and clears the bottom word of the Dz operand
with zeros. When Dz is a register that has guard bits, the guard bits
are also zeroed. The amount of the shift is specified by the immediate value.
When the shift amount is positive, it shifts left. When the shift amount is
negative, it shifts right.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pshl_imm (void)
{
 unsigned short tmp_imm;
 DSP_ALU_SRC1 = DSP_REG[ex2_dz_no];
 switch (ex2_dz_no)
 {
 case 0x0:
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x1:
 DSP_ALU_SRC1G = A1G;
 break;
 default:
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 }
 tmp_imm = ((EX2_LW >> 4) & MASK0000003F); // bit[9:4]
 if ((tmp_imm & MASK0020) == 0)
 {
 // Left Shift 0 <= cnt < 16
 char cnt = tmp_imm & MASK001F;
 if (cnt > 16)
 {
 printf (""\nPSHL Dz,#Imm,Dz Error! #Imm=%6X exceed range.\n"", tmp_imm);
 exit ();
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW << cnt--;
 carry_bit = ((DSP_ALU_SRC1_HW << cnt) & MASK8000) == 0x8000;
 }
 else
 {
 // Right Shift 0 < cnt <= 16
 char cnt = (~tmp_imm & MASK001F) + 1;
 if (cnt > 16)
 {
 printf (""\nPSHL Dz,#Imm,Dz Error! #Imm=%6X exceed range.\n"", tmp_imm);
 exit ();
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW >> cnt--;
 carry_bit = ((DSP_ALU_SRC1_HW >> cnt) & MASK0001) == 0x1;
 }
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 A0G = 0x0; // clear Guard bits
 else if (ex2_dz_no == 1)
 A1G = 0x0;
 negative_bit = DSP_ALU_DST_MSB;
 zero_bit = DSP_ALU_DST_HW == 0;
 overflow_bit = 0x0;
 #include ""shift_dc_bit.c""
}"
"shld Rm,Rn",0100nnnnmmmm1101,"If Rm >= 0: Rn << Rm -> Rn
If Rm < 0: Rn >> |Rm| -> [0 -> Rn]","Logically shifts the contents of general register Rn. General register Rm specifies the shift direction and the number of bits to be shifted. Rn register contents are shifted to the left if the Rm register value is positive, and to the right if negative. In a shift to the right, 0s are added at the upper end. The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of the Rm register. If the value is negative (MSB = 1), the Rm register is represented as a two's complement. The left shift range is 0 to 31, and the right shift range, 1 to 32.","void SHLD (int m, int n) {
 int sgn = R[m] & 0x80000000;
 if (sgn == 0)
 R[n] <<= (R[m] & 0x1F);
 else if ((R[m] & 0x1F) == 0)
 R[n] = 0;
 else
 R[n] = (unsigned)R[n] >> ((~R[m] & 0x1F) + 1);
 PC += 2;
}"
"sts A0,Rn",0000nnnn01111010,A0 -> Rn,Stores DSP register A0 in the destination.,"void STSA0 (int n) {
 R[n] = A0;
 PC += 2;
}"
"sts.l A0,@-Rn",0100nnnn01100010,"Rn-4 -> Rn, A0 -> (Rn)",Stores DSP register A0 in the destination.,"void STSMA0 (int n) {
 R[n] -= 4;
 Write_32 (R[n], A0);
 PC += 2;
}"
"sts X0,Rn",0000nnnn10001010,X0 -> Rn,Stores DSP register X0 in the destination.,"void STSX0 (int n) {
 R[n] = X0;
 PC += 2;
}"
"sts.l X0,@-Rn",0100nnnn10000010,"Rn-4 -> Rn, X0 -> (Rn)",Stores DSP register X0 in the destination.,"void STSMX0 (int n) {
 R[n] -= 4;
 Write_32 (R[n], X0);
 PC += 2;
}"
"sts X1,Rn",0000nnnn10011010,X1 -> Rn,Stores DSP register X1 in the destination.,"void STSX1 (int n) {
 R[n] = X1;
 PC += 2;
}"
"sts.l X1,@-Rn",0100nnnn10010010,"Rn-4 -> Rn, X1 -> (Rn)",Stores DSP register X1 in the destination.,"void STSMX1 (int n) {
 R[n] -= 4;
 Write_32 (R[n], X1);
 PC += 2;
}"
"sts Y0,Rn",0000nnnn10101010,Y0 -> Rn,Stores DSP register Y0 in the destination.,"void STSY0 (int n) {
 R[n] = Y0;
 PC += 2;
}"
"stc SPC,Rn",0000nnnn01000010,SPC -> Rn,Stores control register SPC in the destination.,void STCSPC (int n) { R[n] = SPC; PC += 2; }
"stc.l SPC,@-Rn",0100nnnn01000011,"Rn-4 -> Rn, SPC -> (Rn)",Stores control register SPC in the destination.,"void STCMSPC (int n) { R[n] -= 4; Write_32 (R[n], SPC); PC += 2; }"
"stc DBR,Rn",0000nnnn11111010,DBR -> Rn,Stores control register DBR in the destination.,void STCDBR (int n) { R[n] = DBR; PC += 2; }
"stc.l DBR,@-Rn",0100nnnn11110010,"Rn-4 -> Rn, DBR -> (Rn)",Stores control register DBR in the destination.,"void STCMDBR (int n) { R[n] -= 4; Write_32 (R[n], DBR); PC += 2; }"
"stc Rm_BANK,Rn",0000nnnn1mmm0010,Rm_BANK -> Rn (m = 0-7),"Stores a banked general register in the destination. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.",void STCRm_BANK (int n) { R[n] = Rm_BANK; PC += 2; }
"stc.l Rm_BANK,@-Rn",0100nnnn1mmm0011,"Rn-4 -> Rn, Rm_BANK -> (Rn) (m = 0-7)","Stores a banked general register in the destination. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.","void STCMRm_BANK (int n) { R[n] -= 4; Write_32 (R[n], Rm_BANK); PC += 2; }"
"sts MACH,Rn",0000nnnn00001010,MACH -> Rn,Stores system register MACH in the destination.,void STSMACH (int n) { R[n] = MACH; #if SH1 if ((R[n] & 0x00000200) == 0) R[n] &= 0x000003FF; else R[n] |= 0xFFFFFC00; #endif PC += 2; }
"pneg Sy,Dz",111110********** 1110100100yyzzzz,0 - Sy -> Dz,"Reverses the sign. Subtracts the Sy operand from 0 and stores the result in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pneg_sy (void) {
 DSP_ALU_SRC1 = 0;
 DSP_ALU_SRC1G = 0;
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_minus_dc_bit.c""
}"
"movml.l @R15+,Rn",0100nnnn11110101,"(R15) -> R0, R15+4 -> R15 (R15) -> R1, R15+4 -> R15 ... (R15) -> Rn","Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (R0 to Rn/Rm) not exceeding the specified register number and memory with the contents of R15 as its address. If R15 is specified, PR is transferred instead of R15. That is, when nnnn(mmmm) = 1111 is specified, R0 to R14 and PR are the general registers subject to transfer.",void MOVLPML (int n) { for (int i = 0; i <= n; i++) { if (i == 15) PR = Read_32 (R[15]); else R[i] = Read_32 (R[15]); R[15] += 4; } PC += 2; }
"movmu.l Rm,@-R15",0100mmmm11110000,"R15-4 -> R15, PR -> (R15) R15-4 -> R15, R14 -> (R15) ... R15-4 -> R15, Rm -> (R15)","Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (Rn/Rm to R14, PR) not lower than the specified register number and memory with the contents of R15 as its address. If R15 is specified, PR is transferred instead of R15.","void MOVLMMU (int m) { Write_32 (R[15] - 4, PR); R[15] -= 4; for (int i = 14; i >= m; i--) { Write_32 (R[15] - 4, R[i]); R[15] -= 4; } PC += 2; }"
"movmu.l @R15+,Rn",0100nnnn11110100,"(R15) -> Rn, R15+4 -> R15 (R15) -> Rn+1, R15+4 -> R15 ... (R15) -> R14, R15+4 -> R15 (R15) -> PR","Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (Rn/Rm to R14, PR) not lower than the specified register number and memory with the contents of R15 as its address. If R15 is specified, PR is transferred instead of R15.",void MOVLPMU (int n) { for (int i = n; i <= 14; i++) { R[i] = Read_32 (R[15]); R[15] += 4; } PR = Read_32 (R[15]); R[15] += 4; PC += 2; }
movrt Rn,0000nnnn00111001,~T -> Rn,Reverses the T bit and then stores the resulting value in general register Rn. The value of Rn is 0 when T = 1 and 1 when T = 0.,void MOVRT (int n) { if (T == 1) R[n] = 0x00000000; else R[n] = 0x00000001; PC += 2; }
movt Rn,0000nnnn00101001,T -> Rn,Stores the T bit in general register Rn. The value of Rn is 1 when T = 1 and 0 when T = 0.,void MOVT (int n) { if (T == 1) R[n] = 0x00000001; else R[n] = 0x00000000; PC += 2; }
nott,0000000001101000,~T -> T,"Inverts the T bit, then stores the resulting value in the T bit.",void NOTT (void) { if (T == 1) T = 0; else T = 1; PC += 2; }
"swap.b Rm,Rn",0110nnnnmmmm1000,Rm -> swap lower 2 bytes -> Rn,Swaps the upper and lower parts of the contents of general register Rm and stores the result in Rn. The 8 bits from bit 15 to bit 8 of Rm are swapped with the 8 bits from bit 7 to bit 0. The upper 16 bits of Rm are transferred directly to the upper 16 bits of Rn.,"void SWAPB (int m, int n) { unsigned long temp0, temp1; temp0 = R[m] & 0xFFFF0000; temp1 = (R[m] & 0x000000FF) << 8; R[n] = (R[m] & 0x0000FF00) >> 8; R[n] = R[n] | temp1 | temp0; PC += 2; }"
"dct pdec Sx,Dz",111110********** 10001010xx00zzzz,"If DC = 1: MSW of Sx - 1 -> MSW of DZ, clear LSW of Dz
Else: nop","Conditionally subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pdec_sx_dct (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"movx.w @Ax+Ix,Dx",111100A*D*0*11**,"(Ax) -> MSW of Dx, 0 -> LSW of Dx, Ax+Ix -> Ax",Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for X memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros.,MSW of Dx = (Ax); LSW of Dx = 0; Ax = Ax + Ix
"movx.w Da,@Ax",111100A*D*1*01**,MSW of Da -> (Ax),Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register.,(Ax) = MSW of Da
"movx.w Da,@Ax+",111100A*D*1*10**,"MSW of Da -> (Ax), Ax+2 -> Ax",Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register.,(Ax) = MSW of Da; Ax = Ax + 2
"movx.w Da,@Ax+Ix",111100A*D*1*11**,"MSW of Da -> (Ax), Ax+Ix -> Ax",Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register.,(Ax) = MSW of Da; Ax = Ax + Ix
nopy,111100*0*0*0**00,No Operation,No access operation for Y memory.,No operation performed.
"dcf pdmsb Sy,Dz",111110********** 1011111100yyzzzz,"If DC = 0: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pdmsb_sy_dcf (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"pcmp Sx,Sy",111110********** 10000100xxyy0000,Sx - Sy,"Subtracts the contents of the Sy operand from the Sx operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pcmp (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
negative_bit = DSP_ALU_DSTG_BIT7;
 zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_minus_dc_bit.c""
}"
"plds Dz,MACL",111110********** 111111010000zzzz,Dz -> MACL,"Stores the Dz operand in the MACL register. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void plds_macl (void) { MACL = DSP_REG[ex2_dz_no]; }
"mov.w R0,@(disp,GBR)",11000001dddddddd,R0 -> (disp*2 + GBR),"Transfers the source operand to the destination. The 8-bit displacement is multiplied by two after zero-extension, enabling a range up to +510 bytes to be specified.","void MOVWSG (int d) { unsigned int disp = (0x000000FF & d); Write_16 (GBR + (disp << 1), R[0]); PC += 2; }"
"mov.l R0,@(disp,GBR)",11000010dddddddd,R0 -> (disp*4 + GBR),"Transfers the source operand to the destination. The 8-bit displacement is multiplied by four after zero-extension, enabling a range up to +1020 bytes to be specified.","void MOVLSG (int d) { unsigned int disp = (0x000000FF & (long)d); Write_32 (GBR + (disp << 2), R[0]); PC += 2; }"
"movco.l R0,@Rn",0000nnnn01110011,LDST -> T If (T == 1): R0 -> Rn 0 -> LDST,"MOVCO is used in combination with MOVLI to realize an atomic read-modify-write operation in a single processor. This instruction copies the value of the LDST flag to the T bit. When the T bit is set to 1, the value of R0 is stored at the address in Rm. If the T bit is cleared to 0, the value is not stored at the address in Rm. Finally, the LDST flag is cleared to 0. Since the LDST flag is cleared by an instruction or exception, storage by the MOVCO instruction only proceeds when no interrupt or exception has occurred between the execution of the MOVLI and MOVCO instructions.","void MOVCO (int n) { T = LDST; if (T == 1) Write_32 (R[n], R[0]); LDST = 0; PC += 2 }"
"movli.l @Rm,R0",0000mmmm01100011,1 -> LDST (Rm) -> R0 When interrupt/exception occured: 0 -> LDST,"MOVLI is used in combination with MOVCO to realize an atomic read-modify-write operation in a single processor. This instruction sets the LDST flag to 1 and reads the four bytes of data indicated by Rm into R0. If, however, an interrupt or exception occurs, LDST is cleared to 0. Storage by the MOVCO instruction only proceeds when the instruction is executed after the LDST bit has been set by the MOVLI instruction and not cleared by an interrupt or other exception. When LDST has been cleared to 0, the MOVCO instruction clears the T bit and does not proceed with storage.",void MOVLINK (int m) { LDST = 1; R[0] = Read_32 (R[m]); PC += 2 }
"movua.l @Rm,R0",0100mmmm10101001,(Rm) -> R0 Load non-boundary alignment data,"Loads the longword of data from the effective address indicated by the contents of Rm in memory to R0. The address is not restricted to longword boundaries address (4n). This instruction allows loading from non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). Data address error exceptions do not occur when access is to non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3).","void MOVUAL (int m) { Read_Unaligned_32 (R0, R[m]); PC += 2; }"
"movua.l @Rm+,R0",0100mmmm11101001,"(Rm) -> R0, Rm + 4 -> Rm Load non-boundary alignment data","Loads the longword of data from the effective address indicated by the contents of Rm in memory to R0. The address is not restricted to longword boundaries address (4n). This instruction allows loading from non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). Data address error exceptions do not occur when access is to non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3).","void MOVUALP (int m) { Read_Unaligned_32 (R0,R[m]); if (m != 0) R[m] += 4; PC += 2; }"
"movml.l Rm,@-R15",0100mmmm11110001,"R15-4 -> R15, Rm -> (R15) R15-4 -> R15, Rm-1 -> (R15) ... ... R15 - 4 -> R15, R0 -> (R15) Note: When Rm = R15, read Rm as PR","Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (R0 to Rn/Rm) not exceeding the specified register number and memory with the contents of R15 as its address. If R15 is specified, PR is transferred instead of R15. That is, when nnnn(mmmm) = 1111 is specified, R0 to R14 and PR are the general registers subject to transfer.","void MOVLMML (int m) { for (int i = m; i >= 0; i--) { if (i == 15) Write_32 (R[15] - 4, PR); else Write_32 (R[15] - 4, R[i]); R[15] -= 4; } PC += 2; }"
"movs.l @-As,Ds",111101AADDDD0010,"As-4 -> As, (As) -> Ds","Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.l @As,Ds",111101AADDDD0110,(As) -> Ds,"Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.l @As+,Ds",111101AADDDD1010,"(As) -> Ds, As+4 -> As","Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.l @As+Is,Ds",111101AADDDD1110,"(As) -> Ds, As+Is -> As","Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.l Ds,@-As",111101AADDDD0011,"As-4 -> As, Ds -> (As)","Transfers the source operand data to the destination. The transferred data is a longword.
Note: When one of the guard bit registers A0G and A1G is the source operand it is sign extended and stored as a word.",
"movs.l Ds,@As",111101AADDDD0111,Ds -> (As),"Transfers the source operand data to the destination. The transferred data is a longword.
Note: When one of the guard bit registers A0G and A1G is the source operand it is sign extended and stored as a word.",
"movs.l Ds,@As+",111101AADDDD1011,"Ds -> (As), As+4 -> As","Transfers the source operand data to the destination. The transferred data is a longword.
Note: When one of the guard bit registers A0G and A1G is the source operand it is sign extended and stored as a word.",
"fcmp/eq FRm,FRn",1111nnnnmmmm0100,If FRn = FRm: 1 -> T Else: 0 -> T,"Arithmetically compares the two single-precision floating-point numbers in FRn and FRm, and stores 1 in the T bit if they are equal, or 0 otherwise.","void FCMP_EQ (int m, int n) { PC += 2; clear_cause (); if (fcmp_chk_single (m, n) == INVALID) fcmp_invalid (); else if (fcmp_chk_single (m, n) == EQ) T = 1; else T = 0; }"
"fcmp/gt FRm,FRn",1111nnnnmmmm0101,If FRn > FRm: 1 -> T Else: 0 -> T,"Arithmetically compares the two single-precision floating-point numbers in FRn and FRm, and stores 1 in the T bit if FRn > FRm, or 0 otherwise.","void FCMP_GT (int m, int n) { PC += 2; clear_cause (); if (fcmp_chk_single (m, n) == INVALID || fcmp_chk_single (m, n) == UO) fcmp_invalid (); else if (fcmp_chk_single (m, n) == GT) T = 1; else T = 0; }"
"float FPUL,FRn",1111nnnn00101101,(float)FPUL -> FRn,"Taking the contents of FPUL as a 32-bit integer, converts this integer to a single-precision floating-point number and stores the result in FRn.",void FLOAT_single (int n) { union { double d; int l[2]; } tmp; PC += 2; clear_cause (); FR[n] = FPUL; // convert from integer to float tmp.d = FPUL; if (tmp.l[1] & 0x1FFFFFFF) inexact(); }
"ftrc FRm,FPUL",1111mmmm00111101,(long)FRm -> FPUL,"Converts the single-precision floating-point number in FRm to a 32-bit integer, and stores the result in FPUL.","void FTRC_single (int m) { PC += 2; clear_cause (); switch (ftrc_single_type_of (m)) { case NORM: FPUL = FR[m]; // Convert float to integer break; case PINF: ftrc_invalid (0, &FPUL); break; case NINF: ftrc_invalid (1, &FPUL); break; } }"
"fipr FVm,FVn",1111nnmm11101101,"inner_product (FVm, FVn) -> FR[n+3]","Calculates the inner products of the 4-dimensional single-precision floating-point vector indicated by FVn and FVm, and stores the results in FR[n + 3].","void FIPR (int m, int n) { if (FPSCR_PR == 0) { PC += 2; clear_cause (); fipr (m,n); } else undefined_operation (); }"
"fmov.s FRm,@Rn",1111nnnnmmmm1010,FRm -> (Rn),Transfers FRm contents to memory at address indicated by Rn.,"void FMOV_STORE (int m, int n) {
 Write_32 (R[n], FR[m]);
 PC += 2;
}"
"fmov.s @Rm+,FRn",1111nnnnmmmm1001,"(Rm) -> FRn, Rm+4 -> Rm","Transfers contents of memory at address indicated by Rm to FRn, and adds 4 to Rm.","void FMOV_RESTORE (int m, int n) {
 FR[n] = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"fmov.s FRm,@-Rn",1111nnnnmmmm1011,"Rn-4 -> Rn, FRm -> (Rn)","Subtracts 4 from Rn, and transfers FRm contents to memory at address indicated by resulting Rn value.","void FMOV_SAVE (int m, int n) {
 Write_32 (R[n] - 4, FR[m]);
 R[n] -= 4;
 PC += 2;
}"
"fmov.s @(R0,Rm),FRn",1111nnnnmmmm0110,(R0 + Rm) -> FRn,Transfers contents of memory at address indicated by (R0 + Rm) to FRn.,"void FMOV_INDEX_LOAD (int m, int n) {
 FR[n] = Read_32 (R[0] + R[m]);
 PC += 2;
}"
"fmov.s FRm,@(R0,Rn)",1111nnnnmmmm0111,FRm -> (R0 + Rn),Transfers FRm contents to memory at address indicated by (R0 + Rn).,"void FMOV_INDEX_STORE (int m, int n) {
 Write_32 (R[0] + R[n], FR[m]);
 PC += 2;
}"
"fmov.s @(disp12,Rm),FRn",0011nnnnmmmm0001 0111dddddddddddd,(disp*4 + Rm) -> FRn,Transfers memory contents at the address indicated by (disp + Rn) to FRn.,"void FMOV_INDEX_DISP12_LOAD (int m, int n, int d) {
 long disp = (0x00000FFF & (long)d);
 FR[n] = Read_32 (R[m] + (disp << 2));
 PC += 4;
}"
"fmov.s FRm,@(disp12,Rn)",0011nnnnmmmm0001 0011dddddddddddd,FRm -> (disp*4 + Rn),Transfers FRm contents to memory at the address indicated by (disp + Rn).,"void FMOV_INDEX_DISP12_STORE (int m, int n, int d) {
 long disp = (0x00000FFF & (long)d);
 Write_32 (R[n] + (disp << 2), FR[m]);
 PC += 4;
}"
"prnd Sx,Dz",111110********** 10011000xx00zzzz,"Sx + 0x00008000 -> Dz, clear LSW of Dz","Does rounding. Adds the immediate data 0x00008000 to the contents of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of Dz with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void prnd_sx (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST = (DSP_ALU_SRC1 + DSP_ALU_SRC2) & MASKFFFF0000;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_plus_dc_bit.c""
}"
"fdiv FRm,FRn",1111nnnnmmmm0011,FRn / FRm -> FRn,"Arithmetically divides the single-precision floating-point number in FRn by the single-precision floating-point number in FRm, and stores the result in FRn.","void FDIV (int m, int n) {
 PC += 2;
 clear_cause ();
 if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
 invalid (n);
 else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
 qnan (n);
 else
 switch (data_type_of (m))
 {
 case NORM:
 switch (data_type_of (n))
 {
 case PINF:
 case NINF:
 inf (n, sign_of (m) ^ sign_of (n));
 break;
 case PZERO:
 case NZERO:
 zero (n, sign_of (m) ^ sign_of (n));
 break;
 case DENORM:
 set_E ();
 break;
 default:
 normal_fdiv_single (m, n);
 break;
 }
 break;
 case PZERO:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 invalid (n);
 break;
 case PINF:
 case NINF:
 break;
 default:
 dz (n, sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 case NZERO:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 invalid (n);
 break;
 case PINF:
 inf (n, 1);
 break;
 case NINF:
 inf (n, 0);
 break;
 default:
 dz (FR[n], sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 case DENORM:
 set_E ();
 break;
 case PINF:
 case NINF:
 switch (data_type_of (n))
 {
 case DENORM:
 set_E ();
 break;
 case PINF:
 case NINF:
 invalid (n);
 break;
 default:
 zero (n, sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 }
}
void normal_fdiv_single (int m, int n) {
 union
 {
 float f;
 int l;
 } dstf, tmpf;
 union
 {
 double d;
 int l[2];
 } tmpd;
 tmpf.f = FR[n]; // save destination value
 dstf.f /= FR[m]; // round toward nearest or even
 tmpd.d = dstf.f; // convert single to double
 tmpd.d *= FR[m];
 if (tmpf.f != tmpd.d)
 set_I ();
 if (tmpf.f < tmpd.d && FPSCR_RM == 1)
 dstf.l -= 1; // round toward zero
 check_single_exception (&FR[n], dstf.f);
}"
"padd Sx,Sy,Du
pmuls Se,Sf,Dg",111110********** 0111eeffxxyygguu,"Sx + Sy -> Du
MSW of Se * MSW of Sf -> Dg",Adds the contents of the Sx and Sy operands and stores the result in the Du operand. The contents of the top word of the Se and Sf operands are multiplied as signed and the result stored in the Dg operand. These two processes are executed simultaneously in parallel.,"void padd_pmuls (void)
{
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 switch (EX2_DU)
 {
 case 0x0:
 X0 = DSP_ALU_DST;
 negative_bit = DSP_ALU_DSTG_BIT7;
 zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
 break;
 case 0x1:
 Y0 = DSP_ALU_DST;
 negative_bit = DSP_ALU_DSTG_BIT7;
 zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
 break;
 case 0x2:
 A0 = DSP_ALU_DST;
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 negative_bit = DSP_ALU_DSTG_BIT7;
 zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
 break;
 case 0x3:
 A1 = DSP_ALU_DST;
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 negative_bit = DSP_ALU_DSTG_BIT7;
 zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
 break;
 }
 #include ""fixed_pt_plus_dc_bit.c""
}"
"pinc Sy,Dz",111110********** 1011100100yyzzzz,"MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz","Adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pinc_sy (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 #include ""integer_unconditional_update.c""
 #include ""integer_plus_dc_bit.c""
}"
"pneg Sx,Dz",111110********** 11001001xx00zzzz,0 - Sx -> Dz,"Reverses the sign. Subtracts the Sx operand from 0 and stores the result in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pneg_sx (void) {
 DSP_ALU_SRC1 = 0;
 DSP_ALU_SRC1G = 0;
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC2 = X0;
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = X1;
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC2 = A0;
 DSP_ALU_SRC2G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC2 = A1;
 DSP_ALU_SRC2G = A1G;
 break;
 }
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_minus_dc_bit.c""
}"
"pdmsb Sy,Dz",111110********** 1011110100yyzzzz,"Sy data MSB position -> MSW of Dz, clear LSW of Dz","Finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pdmsb_sy (void) {
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 overflow_bit = 0;
 #include ""integer_unconditional_update.c""
 #include ""integer_plus_dc_bit.c""
}"
"lds Rm,MACL",0100mmmm00011010,Rm -> MACL,Stores the source operand into the system register MACL.,"void LDSMACL (int m) {
 MACL = R[m];
 PC += 2;
}"
"lds.l @Rm+,MACL",0100mmmm00010110,"(Rm) -> MACL, Rm+4 -> Rm",Stores the source operand into the system register MACL.,"void LDSMMACL (int m) {
 MACL = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"lds Rm,PR",0100mmmm00101010,Rm -> PR,Stores the source operand into the system register PR.,"void LDSPR (int m) {
 PR = R[m];
 PC += 2;
}"
"lds.l @Rm+,PR",0100mmmm00100110,"(Rm) -> PR, Rm+4 -> Rm",Stores the source operand into the system register PR.,"void LDSMPR (int m) {
 PR = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"lds Rm,DSR",0100mmmm01101010,Rm -> DSR,Stores the source operand into the DSP register DSR.,"void LDSDSR (int m) {
 DSR = R[m] & 0x0000000F;
 PC += 2;
}"
"lds.l @Rm+,DSR",0100mmmm01100110,"(Rm) -> DSR, Rm+4 -> Rm",Stores the source operand into the DSP register DSR.,"void LDSMDSR (int m) {
 DSR = Read_32 (R[m]) & 0x0000000F;
 R[m] += 4;
 PC += 2;
}"
"lds Rm,A0",0100mmmm01110110,Rm -> A0,Stores the source operand into the DSP register A0. The MSB of the data is copied into A0G.,"void LDSA0 (int m) {
 A0 = R[m];
 if ((A0 & 0x80000000) == 0)
 A0G = 0x00;
 else
 A0G = 0xFF;
 PC+=2;
}"
"fdiv DRm,DRn",1111nnn0mmm00011,DRn / DRm -> DRn,"Arithmetically divides the double-precision floating-point number in DRn by the double-precision floating-point number in DRm, and stores the result in DRn.","void FDIV (int m, int n) {
 PC += 2;
 clear_cause ();
 if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
 invalid (n);
 else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
 qnan (n);
 else
 switch (data_type_of (m))
 {
 case NORM:
 switch (data_type_of (n))
 {
 case PINF:
 case NINF:
 inf (n, sign_of (m) ^ sign_of (n));
 break;
 case PZERO:
 case NZERO:
 zero (n, sign_of (m) ^ sign_of (n));
 break;
 case DENORM:
 set_E ();
 break;
 default:
 normal_fdiv_double (m, n);
 break;
 }
 break;
 case PZERO:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 invalid (n);
 break;
 case PINF:
 case NINF:
 break;
 default:
 dz (n, sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 case NZERO:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 invalid (n);
 break;
 case PINF:
 inf (n, 1);
 break;
 case NINF:
 inf (n, 0);
 break;
 default:
 dz (FR[n], sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 case DENORM:
 set_E ();
 break;
 case PINF:
 case NINF:
 switch (data_type_of (n))
 {
 case DENORM:
 set_E ();
 break;
 case PINF:
 case NINF:
 invalid (n);
 break;
 default:
 zero (n, sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 }
}
void normal_fdiv_double (int m, int n) {
 union
 {
 double d;
 int l[2];
 } dstd, tmpd;
 union
 {
 int double x;
 int l[4];
 } tmpx;
 tmpd.d = DR[n >> 1]; // save destination value
 dstd.d /= DR[m >> 1]; // round toward nearest or even
 tmpx.x = dstd.d; // convert double to int double
 tmpx.x *= DR[m >> 1];
 if (tmpd.d != tmpx.x)
 set_I ();
 if (tmpd.d < tmpx.x && FPSCR_RM == 1)
 {
 dstd.l[1] -= 1; // round toward zero
 if (dstd.l[1] == 0xFFFFFFFF)
 dstd.l[0] -= 1;
 }
 check_double_exception (&DR[n >> 1], dstd.d);
}"
dcf pclr Dz,111110********** 100011110000zzzz,"If DC = 0: 0x00000000 -> Dz
Else: nop","Conditionally clears the Dz operand. The instruction is executed when the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pclr_dcf (void)
{
 if (DC == 0)
 DSP_REG[ex2_dz_no] = 0x0;
}"
"psha Sx,Sy,Dz",111110********** 10010001xxyyzzzz,"If Sy >= 0: Sx << Sy -> Dz
If Sy < 0: Sx >> Sy -> Dz","Arithmetically shifts the contents of the Sx or Dz operand and stores the result in the Dz operand. The amount of the shift is specified by the Sy operand. When the shift amount is positive, it shifts left. When the shift amount is negative, it shifts right. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void psha (void)
{
 switch (EX2_SX)
 {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0 & MASK007F0000;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1 & MASK007F0000;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0 & MASK007F0000;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1 & MASK007F0000;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 if ((DSP_ALU_SRC2_HW & MASK0040) == 0)
 {
 // Left Shift 0 <= cnt <= 32
 char cnt = DSP_ALU_SRC2_HW & MASK003F;
 if (cnt > 32)
 {
 printf (""\nPSHA Sz,Sy,Dz Error! Shift %2X exceed range.\n"", cnt);
 exit ();
 }
 DSP_ALU_DST = DSP_ALU_SRC1 << cnt;
 DSP_ALU_DSTG = ((DSP_ALU_SRC1G << cnt)
 | (DSP_ALU_SRC1 >> (32 - cnt))) & MASK000000FF;
 carry_bit = ((DSP_ALU_DSTG & MASK00000001) == 0x1);
 }
 else
 {
 // Right Shift 0 < cnt <= 32
 char cnt = (~DSP_ALU_SRC2_HW & MASK003F) + 1;
 if (cnt > 32)
 {
 printf (""\nPSHA Sz,Sy,Dz Error! shift -%2X exceed range.\n"", cnt);
 exit ();
 }
 if ((cnt > 8) && DSP_ALU_SRC1G_BIT7)
 {
 // MSB copy
 DSP_ALU_DST = (DSP_ALU_SRC1 >> 8) | (DSP_ALU_SRC1G << (32 - 8));
 DSP_ALU_DST = (long)DSP_ALU_DST >> (cnt - 8);
 }
 else
 DSP_ALU_DST = (DSP_ALU_SRC1 >> cnt) | (DSP_ALU_SRC1G << (32 - cnt));
 DSP_ALU_DSTG_LSB8 = (char)DSP_ALU_SRC1G_LSB8 >> cnt--;
 carry_bit = ((DSP_ALU_SRC1 >> cnt) & MASK00000001) == 0x1;
 }
 overflow_bit = ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""shift_dc_bit.c""
}"
"ftrc DRm,FPUL",1111mmm000111101,(long)DRm -> FPUL,"Converts the double-precision floating-point number in DRm to a 32-bit integer, and stores the result in FPUL.","void FTRC_double (int m) {
 PC += 2;
 clear_cause ();
 switch (ftrc_double_type_of (m))
 {
 case NORM:
 FPUL = DR[m >> 1]; // Convert double to integer
 break;
 case PINF:
 ftrc_invalid (0, &FPUL);
 break;
 case NINF:
 ftrc_invalid (1, &FPUL);
 break;
 }
}
int ftrc_double_type_of (int m) {
 if (sign_of (m) == 0)
 {
 if (FR_HEX[m] > 0x7FF00000
 || (FR_HEX[m] == 0x7FF00000 && FR_HEX[m+1] != 0x00000000))
 return NINF; // NaN
 else if (DR_HEX[m >> 1] >= POS_INT_DOUBLE_RANGE)
 return PINF; // out of range, +INF
 else
 return NORM; // +0, +NORM
 }
 else
 {
 if ((DR_HEX[m >> 1] & 0x7FFFFFFFFFFFFFFF) >= NEG_INT_DOUBLE_RANGE)
 return NINF; // out of range, +INF, NaN
 else
 return NORM; // -0, -NORM
 }
}
void ftrc_invalid (int sign, int* result) {
 set_V ();
 if ((FPSCR & ENABLE_V) == 0)
 {
 if (sign == 0)
 *result = 0x7FFFFFFF;
 else
 *result = 0x80000000;
 }
 else
 fpu_exception_trap ();
}"
"dct pdmsb Sx,Dz",111110********** 10011110xx00zzzz,"If DC = 1: Sx data MSB position -> MSW of Dz, clear LSW of Dz
Else: nop","Conditionally finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pdmsb_sx_dct (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"pdec Sx,Dz",111110********** 10001001xx00zzzz,"MSW of Sx - 1 -> MSW of Dz, clear LSW of Dz","Subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pdec_sx (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 #include ""integer_unconditional_update.c""
 #include ""integer_minus_dc_bit.c""
}"
"dcf pneg Sx,Dz",111110********** 11001011xx00zzzz,If DC = 0: 0 - Sx -> Dz Else: nop,"Conditionally reverses the sign. The instruction is executed if the DC bit is set to 0. Subtracts the Sx operand from 0 and stores the result in the Dz operand. The DC, N, Z, V, and GT bits are not updated.","void pneg_sx_dcf (void) {
 DSP_ALU_SRC1 = 0;
 DSP_ALU_SRC1G = 0;
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC2 = X0;
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = X1;
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC2 = A0;
 DSP_ALU_SRC2G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC2 = A1;
 DSP_ALU_SRC2G = A1G;
 break;
 }
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"dcf pdec Sx,Dz",111110********** 10001011xx00zzzz,"If DC = 0: MSW of Sx - 1 -> MSW of DZ, clear LSW of Dz Else: nop","Conditionally subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pdec_sx_dcf (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"movs.w Ds,@-As",111101AADDDD0001,"As-2 -> As, MSW of Ds -> (As)","Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data.",
"movs.w Ds,@As",111101AADDDD0101,MSW of Ds -> (As),"Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data.",
"movs.w Ds,@As+",111101AADDDD1001,"MSW of Ds -> (As), As+2 -> As","Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data.",
"movs.w Ds,@As+Is",111101AADDDD1101,"MSW of DS -> (As), As+Is -> As","Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data.",
"movs.l @-As,Ds",111101AADDDD0010,"As-4 -> As, (As) -> Ds","Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"dct pcopy Sy,Dz",111110********** 1111101000yyzzzz,If DC = 1: Sy -> Dz Else: nop,"Conditionally stores the Sy operand in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pcopy_sy_dct (void) {
 DSP_ALU_SRC1 = 0;
 DSP_ALU_SRC1G = 0;
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"dct pdec Sx,Dz",111110********** 10001010xx00zzzz,"If DC = 1: MSW of Sx - 1 -> MSW of DZ, clear LSW of Dz
Else: nop","Conditionally subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pdec_sx_dct (void)
{
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SX)
 {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"lds Rm,Y1",0100mmmm10111010,Rm -> Y1,Stores the source operand into the DSP register Y1.,"void LDSY1 (int m) {
 Y1 = R[m];
 PC += 2;
}"
"lds.l @Rm+,Y1",0100nnnn10110110,"(Rm) -> Y1, Rm+4 -> Rm",Stores the source operand into the DSP register Y1.,"void LDSMY1 (int m) {
 Y1 = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
ldtlb,0000000000111000,PTEH/PTEL -> TLB,Loads the contents of the PTEH/PTEL registers into the TLB (translation lookaside buffer) specified by MMUCR.URC (random counter field in the MMC control register).,"void LDTLB (void) {
 #if SH3
 TLB_tag = PTEH;
 TLB_data = PTEL;
 #elif SH4
 TLB[MMUCR.URC].ASID = PTEH & 0x000000FF;
 TLB[MMUCR.URC].VPN = (PTEH & 0xFFFFFC00) >> 10;
 TLB[MMUCR.URC].PPN = (PTEH & 0x1FFFFC00) >> 10;
 TLB[MMUCR.URC].SZ = (PTEL & 0x00000080) >> 6 | (PTEL & 0x00000010) >> 4;
 TLB[MMUCR.URC].SH = (PTEH & 0x00000002) >> 1;
 TLB[MMUCR.URC].PR = (PTEH & 0x00000060) >> 5;
 TLB[MMUCR.URC].WT = (PTEH & 0x00000001);
 TLB[MMUCR.URC].C = (PTEH & 0x00000008) >> 3;
 TLB[MMUCR.URC].D = (PTEH & 0x00000004) >> 2;
 TLB[MMUCR.URC].V = (PTEH & 0x00000100) >> 8;
 #endif
 PC += 2;
}"
"dct pdmsb Sx,Dz",111110********** 10011110xx00zzzz,"If DC = 1: Sx data MSB position -> MSW of Dz, clear LSW of Dz
Else: nop","Conditionally finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pdmsb_sx_dct (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"psubc Sx,Sy,Dz",111110********** 10100000xxyyzzzz,Sx - Sy - DC -> Dz,"Subtracts the contents of the Sy operand and the DC bit from the Sx operand and stores the result in the Dz operand. The DC bit of the DSR register is updated as the borrow flag. The N, Z, V, and GT bits of the DSR register are also updated.","void psubc (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2 - DSPDCBIT;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_dc_always_borrow.c""
}"
"div1 Rm,Rn",0011nnnnmmmm0100,1-step division (Rn / Rm),"Performs 1-digit division (1-step division) of the 32-bit contents of general register Rn (dividend) by the contents of Rm (divisor). The quotient is obtained by repeated execution of this instruction alone or in combination with other instructions. The specified registers and the M, Q, and T bits must not be modified during these repeated executions. In 1-step division, the dividend is shifted 1 bit to the left, the divisor is subtracted from this, and the quotient bit is reflected in the Q bit according to whether the result is positive or negative. Detection of division by zero or overflow is not provided. Check for division by zero and overflow division before executing the division. A remainder operation is not provided. Find the remainder by finding the product of the divisor and the obtained quotient, and subtracting this value from the dividend: remainder = dividend - (divisor * quotient) Initial settings should first be made with the DIV0S or DIV0U instruction. DIV1 is executed once for each bit of the divisor. If a quotient of more than 17 bits is required, place an ROTCL instruction before the DIV1 instruction. See the examples for details of the division sequence.","void DIV1 (int m, int n) { unsigned long tmp0, tmp2; unsigned char old_q, tmp1; old_q = Q; Q = (0x80000000 & R[n]) != 0; tmp2 = R[m]; R[n] <<= 1; R[n] |= (unsigned long)T; if (old_q == 0) { if (M == 0) { tmp0 = R[n]; R[n] -= tmp2; tmp1 = R[n] > tmp0; if (Q == 0) Q = tmp1; else if (Q == 1) Q = tmp1 == 0; } else if (M == 1) { tmp0 = R[n]; R[n] += tmp2; tmp1 = R[n] < tmp0; if (Q == 0) Q = tmp1 == 0; else if (Q == 1) Q = tmp1; } } else if (old_q == 1) { if (M == 0) { tmp0 = R[n]; R[n] += tmp2; tmp1 = R[n] < tmp0; if (Q == 0) Q = tmp1; else if (Q == 1) Q = tmp1 == 0; } else if (M == 1) { tmp0 = R[n]; R[n] -= tmp2; tmp1 = R[n] > tmp0; if (Q == 0) Q = tmp1 == 0; else if (Q == 1) Q = tmp1; } } T = (Q == M); PC += 2; }"
"pinc Sx,Dz",111110********** 10011001xx00zzzz,"MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz","Adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pinc_sx (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 #include ""integer_unconditional_update.c""
 #include ""integer_plus_dc_bit.c""
}"
"psub Sx,Sy,Dz",111110********** 10100001xxyyzzzz,Sx - Sy -> Dz,"Subtracts the contents of the Sy operand from the Sx operand and stores the result in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are updated.","void psub (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_minus_dc_bit.c""
}"
"dct pcopy Sx,Dz",111110********** 11011010xx00zzzz,If DC = 1: Sx -> Dz Else: nop,"Conditionally stores the Sx operand in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pcopy_sx_dct (void) {
 switch (EX2_SX)
 {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_SRC2 = 0;
 DSP_ALU_SRC2G = 0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"movs.w @As,Ds",111101AADDDD0100,"(As) -> MSW of Ds, 0 -> LSW of Ds","Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.w @As+,Ds",111101AADDDD1000,"(As) -> MSW of Ds, 0 -> LSW of Ds, As+2 -> As","Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.w @As+Ix,Ds",111101AADDDD1100,"(As) -> MSW of Ds, 0 -> LSW of DS, As+Ix -> As","Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.w Ds,@-As",111101AADDDD0001,"As-2 -> As, MSW of Ds -> (As)","Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data.",
"movs.w Ds,@As",111101AADDDD0101,MSW of Ds -> (As),"Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data.",
"movs.w Ds,@As+",111101AADDDD1001,"MSW of Ds -> (As), As+2 -> As","Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data.",
"movs.w Ds,@As+Is",111101AADDDD1101,"MSW of DS -> (As), As+Is -> As","Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data.",
"prnd Sy,Dz",111110********** 1011100000yyzzzz,"Sy + 0x00008000 -> Dz, clear LSW of Dz","Does rounding. Adds the immediate data 0x00008000 to the contents of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of Dz with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void prnd_sy (void) { switch (EX2_SY) { case 0x0: DSP_ALU_SRC1 = Y0; break; case 0x1: DSP_ALU_SRC1 = Y1; break; case 0x2: DSP_ALU_SRC1 = M0; break; case 0x3: DSP_ALU_SRC1 = M1; break; } if (DSP_ALU_SRC1_MSB) DSP_ALU_SRC1G = 0xFF; else DSP_ALU_SRC1G = 0x0; DSP_ALU_DST = (DSP_ALU_SRC1 + DSP_ALU_SRC2) & MASKFFFF0000; carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB) | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB); DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit; overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV); #include ""fixed_pt_overflow_protection.c"" #include ""fixed_pt_unconditional_update.c"" #include ""fixed_pt_plus_dc_bit.c"" }"
"dcf pneg Sy,Dz",111110********** 1110101100yyzzzz,If DC = 0: 0 - Sy -> Dz Else: nop,"Conditionally reverses the sign. The instruction is executed if the DC bit is set to 0. Subtracts the Sy operand from 0 and stores the result in the Dz operand. The DC, N, Z, V, and GT bits are not updated.","void pneg_sy_dcf (void) {
 DSP_ALU_SRC1 = 0;
 DSP_ALU_SRC1G = 0;
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"ftrv XMTRX,FVn",1111nn0111111101,"transform_vector (XMTRX, FVn) -> FVn","Takes the contents of floating-point registers XF0 to XF15 indicated by XMTRX as a 4-row × 4-column matrix, takes the contents of floating-point registers FR[n] to FR[n + 3] indicated by FVn as a 4-dimensional vector, multiplies the array by the vector, and stores the results in FV[n].",
fsrra FRn,1111nnnn01111101,1.0 / sqrt (FRn) -> FRn,Takes the approximate inverse of the arithmetic square root (absolute error is within ±2^-21) of the single-precision floating-point in FRn and writes the result to FRn.,
"fsca FPUL,DRn",1111nnn011111101,"sin (FPUL) -> FRn
cos (FPUL) -> FR[n+1]","Calculates the sine and cosine approximations of FPUL (absolute error is within ±2^-21) as single-precision floating point values, and places the values of the sine and cosine in FRn and FR[n + 1], respectively.",
fabs DRn,1111nnn001011101,DRn & 0x7FFFFFFFFFFFFFFF -> DRn,"Clears the most significant bit of the contents of floating-point register DRn to 0, and stores the result in DRn.",
fneg DRn,1111nnn001001101,DRn ^ 0x8000000000000000 -> DRn,"Inverts the most significant bit (sign bit) of the contents of floating-point register DRn, and stores the result in DRn.",
"fadd DRm,DRn",1111nnn0mmm00000,DRn + DRm -> DRn,"Arithmetically adds the two double-precision floating-point numbers in DRn and DRm, and stores the result in DRn.",
"fsub DRm,DRn",1111nnn0mmm00001,DRn - DRm -> DRn,"Arithmetically subtracts the double-precision floating-point number in DRm from the double-precision floating-point number in DRn, and stores the result in DRn.",
"ldc Rm,SGR",0100mmmm00111010,Rm -> SGR,Stores a source operand in control register SGR.,void LDCSGR (int m) { SGR = R[m]; PC += 2; }
"ldc.l @Rm+,SGR",0100mmmm00110110,"(Rm) -> SGR, Rm+4 -> Rm",Stores a source operand in control register SGR.,void LDCMSGR (int m) { SGR = Read_32 (R[m]); R[m] += 4; PC += 2; }
"ldc Rm,SSR",0100mmmm00111110,Rm -> SSR,Stores a source operand in control register SSR.,"void LDCSSR (int m) { SSR = R[m], PC += 2; }"
"ldc.l @Rm+,SSR",0100mmmm00110111,"(Rm) -> SSR, Rm+4 -> Rm",Stores a source operand in control register SSR.,void LDCMSSR (int m) { SSR = Read_32 (R[m]); R[m] += 4; PC += 2; }
"ldc Rm,SPC",0100mmmm01001110,Rm -> SPC,Stores a source operand in control register SPC.,void LDCSPC (int m) { SPC = R[m]; PC += 2; }
"ldc.l @Rm+,SPC",0100mmmm01000111,"(Rm) -> SPC, Rm+4 -> Rm",Stores a source operand in control register SPC.,void LDCMSPC (int m) { SPC = Read_32 (R[m]); R[m] += 4; PC += 2; }
"ldc Rm,DBR",0100mmmm11111010,Rm -> DBR,Stores a source operand in control register DBR.,void LDCDBR (int m) { DBR = R[m]; PC += 2; }
braf Rm,0000mmmm00100011,Rm + PC + 4 -> PC (Delayed branch),This is an unconditional branch instruction. The branch destination is address (PC + 4 + Rm).,"void BRAF (int m) {
 unsigned int temp;
 temp = PC;
 PC = PC + 4 + R[m];
 Delay_Slot (temp + 2);
}"
bsr label,1011dddddddddddd,"PC + 4 -> PR, disp*2 + PC + 4 -> PC (Delayed branch)","Branches to address (PC + 4 + displacement * 2), and stores address (PC + 4) in PR. The PC source value is the BSR instruction address.","void BSR (int d) {
 int disp;
 unsigned int temp;
 temp = PC;
 if ((d & 0x800) == 0)
 disp = (0x00000FFF & d);
 else
 disp = (0xFFFFF000 | d);
 PR = PC + 4;
 PC = PC + 4 + (disp << 1);
 Delay_Slot (temp + 2);
}"
bsrf Rm,0000mmmm00000011,"PC + 4 -> PR, Rm + PC + 4 -> PC (Delayed branch)","Branches to address (PC + 4 + Rm), and stores address (PC + 4) in PR. The PC source value is the BSRF instruction address.","void BSRF (int m) {
 unsigned int temp;
 temp = PC;
 PR = PC + 4;
 PC = PC + 4 + R[m];
 Delay_Slot (temp + 2);
}"
jmp @Rm,0100mmmm00101011,Rm -> PC (Delayed branch),Unconditionally makes a delayed branch to the address specified by Rm.,"void JMP (int m) {
 unsigned int temp;
 temp = PC;
 PC = R[m];
 Delay_Slot (temp + 2);
}"
jsr @Rm,0100mmmm00001011,"PC + 4 -> PR, Rm -> PC (Delayed branch)","Makes a delayed branch to the subroutine procedure at the specified address after execution of the following instruction. Return address (PC + 4) is saved in PR, and a branch is made to the address indicated by general register Rm.","void JSR (int m) {
 unsigned int temp;
 temp = PC;
 PR = PC + 4;
 PC = R[m];
 Delay_Slot (temp + 2);
}"
jsr/n @Rm,0100mmmm01001011,"PC + 2 -> PR, Rm -> PC",Branches to a subroutine procedure at the designated address. The contents of PC are stored in PR and execution branches to the address indicated by the contents of general register Rm as 32-bit data.,"void JSRN (int m) {
 unsigned long temp;
 temp = PC;
 PR = PC + 2;
 PC = R[m];
}"
"jsr/n @@(disp8,TBR)",10000011dddddddd,"PC + 2 -> PR, (disp*4 + TBR) -> PC",Branches to a subroutine procedure at the designated address. The contents of PC are stored in PR and execution branches to the address indicated by the address read from memory address (disp × 4 + TBR).,"void JSRNM (int d) {
 long disp = (0x000000FF & d);
 PR = PC + 2;
 PC = Read_32 (TBR + (disp << 2));
}"
"dct pshl Sx,Sy,Dz",111110********** 10000010xxyyzzzz,"If DC = 1 & Sy >= 0: Sx << Sy -> Dz, clear LSW of Dz
If DC = 1 & Sy < 0: Sx >> Sy -> Dz, clear LSW of Dz
If DC = 0: nop","Conditionally logically shifts the top word contents of the Sx operand, stores
the result in the top word of the Dz operand, and clears the bottom word of the
Dz operand with zeros. When Dz is a register that has guard bits, the guard bits
are also zeroed. The amount of the shift is specified by the Sy operand. When
the shift amount is positive, it shifts left. When the shift amount is negative,
it shifts right.
The instruction is executed if the DC bit is set to 1.
The DC, N, Z, V, and GT bits are not updated.","void pshl_dct
{
 switch (EX2_SX)
 {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 break;
 }
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0 & MASK003F0000;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1 & MASK003F0000;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0 & MASK003F0000;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1 & MASK003F0000;
 break;
 }
 if ((DSP_ALU_SRC2_HW & MASK0020) == 0)
 {
 // Left Shift 0 <= cnt <= 16
 char cnt = DSP_ALU_SRC2_HW & MASK001F;
 if (cnt > 16)
 {
 printf (""\nPSHL Sx,Sy,Dz Error! Shift %2X exceed range.\n"", cnt);
 exit ();
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW << cnt--;
 carry_bit = ((DSP_ALU_SRC1_HW << cnt) & MASK8000) == 0x8000;
 }
 else
 {
 // Right Shift 0 < cnt <= 16
 char cnt = (~DSP_ALU_SRC2_HW & MASK000F) + 1;
 if (cnt > 16)
 {
 printf (""\nPSHL Sx,Sy,Dz Error! Shift -%2X exceed range.\n"", cnt);
 exit ();
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW >> cnt--;
 carry_bit = ((DSP_ALU_SRC1_HW >> cnt) & MASK0001) == 0x1;
 }
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 A0G = 0x0; // clear Guard bits
 else if (ex2_dz_no == 1)
 A1G = 0x0;
 }
}"
"dcf por Sx,Sy,Dz",111110********** 10110111xxyyzzzz,"If DC = 0: Sx | Sy -> Dz, clear LSW of Dz Else: nop","Conditionally takes the OR of the top word of the Sx operand and the top word of the Sy operand, stores the result in the top word of the Dz operand, and clears the bottom word of Dz with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.",void por_dcf (void) { switch (EX2_SX) { case 0x0: DSP_ALU_SRC1 = X0; break; case 0x1: DSP_ALU_SRC1 = X1; break; case 0x2: DSP_ALU_SRC1 = A0; break; case 0x3: DSP_ALU_SRC1 = A1; break; } switch (EX2_SY) { case 0x0: DSP_ALU_SRC2 = Y0; break; case 0x1: DSP_ALU_SRC2 = Y1; break; case 0x2: DSP_ALU_SRC2 = M0; break; case 0x3: DSP_ALU_SRC2 = M1; break; } DSP_ALU_DST_HW = DSP_ALU_SRC1_HW | DSP_ALU_SRC2_HW; if (DC == 0) { DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW; DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW if (ex2_dz_no == 0) A0G = 0x0; // /* */ else if (ex2_dz_no == 1) A1G = 0x0; } }
"pxor Sx,Sy,Dz",111110********** 10100101xxyyzzzz,"Sx ^ Sy -> Dz, clear LSW of Dz","Takes the exclusive OR of the top word of the Sx operand and the top word of the Sy operand, stores the result in the top word of the Dz operand, and clears the bottom word of Dz with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pxor (void) { switch (EX2_SX) { case 0x0: DSP_ALU_SRC1 = X0; break; case 0x1: DSP_ALU_SRC1 = X1; break; case 0x2: DSP_ALU_SRC1 = A0; break; case 0x3: DSP_ALU_SRC1 = A1; break; } switch (EX2_SY) { case 0x0: DSP_ALU_SRC2 = Y0; break; case 0x1: DSP_ALU_SRC2 = Y1; break; case 0x2: DSP_ALU_SRC2 = M0; break; case 0x3: DSP_ALU_SRC2 = M1; break; } DSP_ALU_DST_HW = DSP_ALU_SRC1_HW ^ DSP_ALU_SRC2_HW; DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW; DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW if (ex2_dz_no == 0) A0G = 0x0; // clear Guard bits else if (ex2_dz_no == 1) A1G = 0x0; carry_bit = 0x0; negative_bit = DSP_ALU_DST_MSB; zero_bit = (DSP_ALU_DST_HW == 0); overflow_bit = 0x0; #include ""logical_dc_bit.c"" }"
"dct pxor Sx,Sy,Dz",111110********** 10100110xxyyzzzz,"If DC = 1: Sx ^ Sy -> Dz, clear LSW of Dz Else: nop","Conditionally takes the exclusive OR of the top word of the Sx operand and the top word of the Sy operand, stores the result in the top word of the Dz operand, and clears the bottom word of Dz with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.",void pxor_dct (void) { switch (EX2_SX) { case 0x0: DSP_ALU_SRC1 = X0; break; case 0x1: DSP_ALU_SRC1 = X1; break; case 0x2: DSP_ALU_SRC1 = A0; break; case 0x3: DSP_ALU_SRC1 = A1; break; } switch (EX2_SY) { case 0x0: DSP_ALU_SRC2 = Y0; break; case 0x1: DSP_ALU_SRC2 = Y1; break; case 0x2: DSP_ALU_SRC2 = M0; break; case 0x3: DSP_ALU_SRC2 = M1; break; } DSP_ALU_DST_HW = DSP_ALU_SRC1_HW ^ DSP_ALU_SRC2_HW; if (DC == 1) { DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW; DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW if (ex2_dz_no == 0) A0G = 0x0; // clear Guard bits else if (ex2_dz_no == 1) A1G = 0x0; } }
"dcf pxor Sx,Sy,Dz",111110********** 10100111xxyyzzzz,"If DC = 0: Sx ^ Sy -> Dz, clear LSW of Dz Else: nop","Conditionally takes the exclusive OR of the top word of the Sx operand and the top word of the Sy operand, stores the result in the top word of the Dz operand, and clears the bottom word of Dz with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.",void pxor_dcf (void) { switch (EX2_SX) { case 0x0: DSP_ALU_SRC1 = X0; break; case 0x1: DSP_ALU_SRC1 = X1; break; case 0x2: DSP_ALU_SRC1 = A0; break; case 0x3: DSP_ALU_SRC1 = A1; break; } switch (EX2_SY) { case 0x0: DSP_ALU_SRC2 = Y0; break; case 0x1: DSP_ALU_SRC2 = Y1; break; case 0x2: DSP_ALU_SRC2 = M0; break; case 0x3: DSP_ALU_SRC2 = M1; break; } DSP_ALU_DST_HW = DSP_ALU_SRC1_HW ^ DSP_ALU_SRC2_HW; if (DC == 0) { DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW; DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW if (ex2_dz_no == 0) A0G = 0x0; // clear Guard bits else if (ex2_dz_no == 1) A1G = 0x0; } }
"pmuls Se,Sf,Dg",111110********** 0100eeff0000gg00,MSW of Se * MSW of Sf -> Dg,"The contents of the top word of the Se and Sf operands are multiplied as signed and the result stored in the Dg operand. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void pmuls (void) { switch (ee) // Se Operand selection bit (ee) { case 0x0: DSP_M_SRC1 = X0; break; case 0x1: DSP_M_SRC1 = X1; break; case 0x2: DSP_M_SRC1 = Y0; break; case 0x3: DSP_M_SRC1 = A1; break; } switch (ff) // Sf Operand selection bit (ff) { case 0x0: DSP_M_SRC2 = Y0; break; case 0x1: DSP_M_SRC2 = Y1; break; case 0x2: DSP_M_SRC2 = X0; break; case 0x3: DSP_M_SRC2 = A1; break; } if ((SBIT == 1) && (DSP_M_SRC1 == 0x8000) && (DSP_M_SRC2 == 0x8000)) DSP_M_DST = 0x7FFFFFFF; // overflow protection else DSP_M_DST= ((long)(short)DSP_M_SRC1 * (long)(short)DSP_M_SRC2) << 1; if (DSP_M_DST_MSB) DSP_M_DSTG_LSB8 = 0xFF; else DSP_M_DSTG_LSB8 = 0x0; switch (gg) // Dg Operand selection bit (gg) { case 0x0: M0 = DSP_M_DST; break; case 0x1: M1 = DSP_M_DST; break; case 0x2: A0 = DSP_M_DST; if (DSP_M_DSTG_LSB8 == 0x0) A0G=0x0; else A0G = 0xFFFFFFFF; break; case 0x3: A1 = DSP_M_DST; if (DSP_M_DSTG_LSB8 == 0x0) A1G = 0x0; else A1G = 0xFFFFFFFF; break; } }
"pdec Sy,Dz",111110********** 1010100100yyzzzz,"MSW of Sy - 1 -> MSW of Dz, clear LSW of Dz","Subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pdec_sy (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 #include ""integer_unconditional_update.c""
 #include ""integer_minus_dc_bit.c""
}"
"pdmsb Sx,Dz",111110********** 10011101xx00zzzz,"Sx data MSB position -> MSW of Dz, clear LSW of Dz","Finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pdmsb_sx (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 overflow_bit = 0;
 #include ""integer_unconditional_update.c""
 #include ""integer_plus_dc_bit.c""
}"
"fmac FR0,FRm,FRn",1111nnnnmmmm1110,FR0 * FRm + FRn -> FRn,"Arithmetically multiplies the two single-precision floating-point numbers in FR0 and FRm, arithmetically adds the contents of FRn, and stores the result in FRn. When FPSCR.enable.I is set, an FPU exception trap is generated regardless of whether or not an exception has occurred. When FPSCR.enable.O/U is set, FPU exception traps are generated on actual generation by the FPU exception source and on the satisfaction of certain special conditions that apply to this the instruction. When an exception occurs, correct exception information is reflected in FPSCR.cause and FPSCR.flag and FRn is not updated. Appropriate processing should therefore be performed by software.","void FMAC (int m, int n) {
 PC += 2;
 clear_cause ();
 if (FPSCR_PR == 1)
 undefined_operation ();
 else if (data_type_of (0) == sNaN
 || data_type_of (m) == sNaN
 || data_type_of (n) == sNaN)
 invalid (n);
 else if (data_type_of (0) == qNaN || data_type_of (m) == qNaN)
 qnan (n);
 else if (data_type_of (0) == DENORM || data_type_of (m) == DENORM)
 set_E ();
 else
 normal_fmac (m, n);
}"
"mov Rm,Rn",0110nnnnmmmm0011,Rm -> Rn,Transfers the source operand to the destination.,"void MOV (int m, int n) {
 R[n] = R[m];
 PC += 2;
}"
"mov #imm,Rn",1110nnnniiiiiiii,imm -> sign extension -> Rn,"Stores immediate data, sign-extended to longword, in general register Rn.","void MOVI (int i, int n) {
 if ((i & 0x80) == 0)
 R[n] = (0x000000FF & i);
 else
 R[n] = (0xFFFFFF00 | i);
 PC += 2;
}"
"movi20 #imm20,Rn",0000nnnniiii0000 iiiiiiiiiiiiiiii,imm -> sign extension -> Rn,Stores immediate data that has been sign-extended to longword in general register Rn.,"void MOVI20 (int i, int n) {
 if (i & 0x00080000) == 0)
 R[n] = (0x000FFFFF & (long)i);
 else
 R[n] = (0xFFF00000 | (long)i);
 PC += 4;
}"
"movi20s #imm20,Rn",0000nnnniiii0001 iiiiiiiiiiiiiiii,imm << 8 -> sign extension -> Rn,"Shifts immediate data 8 bits to the left and performs sign extension to longword, then stores the resulting data in general register Rn. Using an OR or ADD instruction as the next instruction enables a 28-bit absolute address to be generated.","void MOVI20S (int i, int n) {
 if (i & 0x00080000) == 0)
 R[n] = (0x000FFFFF & (long)i);
 else
 R[n] = (0xFFF00000 | (long)i);
 R[n] <<= 8;
 PC += 4;
}"
"mova @(disp,PC),R0",11000111dddddddd,(disp*4) + (PC & 0xFFFFFFFC) + 4 -> R0,"Stores the effective address of the source operand into general register R0. The 8-bit displacement is zero-extended and quadrupled. Consequently, the relative interval from the operand is PC + 1020 bytes. The PC is the address four bytes after this instruction, but the lowest two bits of the PC are fixed at 00.","void MOVA (int d) {
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & d);
 R[0] = (PC & 0xFFFFFFFC) + 4 + (disp << 2);
 PC += 2;
}"
"mov.w @(disp,PC),Rn",1001nnnndddddddd,(disp*2 + PC + 4) -> sign extension -> Rn,"Stores immediate data, sign-extended to longword, in general register Rn. The data is stored from memory address (PC + 4 + displacement * 2). The 8-bit displacement is multiplied by two after zero-extension, and so the relative distance from the table is in the range up to PC + 4 + 510 bytes. The PC value is the address of this instruction.","void MOVWI (int d, int n) {
 unsigned int disp = (0x000000FF & d);
 R[n] = Read_16 (PC + 4 + (disp << 1));
 if ((R[n] & 0x8000) == 0)
 R[n] &= 0x0000FFFF;
 else
 R[n] |= 0xFFFF0000;
 PC += 2;
}"
"mov.l @(disp,PC),Rn",1101nnnndddddddd,(disp*4 + (PC & 0xFFFFFFFC) + 4) -> sign extension -> Rn,"Stores immediate data, sign-extended to longword, in general register Rn. The data is stored from memory address (PC + 4 + displacement * 4). The 8-bit displacement is multiplied by four after zero-extension, and so the relative distance from the operand is in the range up to PC + 4 + 1020 bytes. The PC value is the address of this instruction. A value with the lower 2 bits adjusted to 00 is used in address calculation.","void MOVLI (int d, int n) {
 unsigned int disp = (0x000000FF & d);
 R[n] = Read_32 ((PC & 0xFFFFFFFC) + 4 + (disp << 2));
 PC += 2;
}"
"pdmsb Sy,Dz",111110********** 1011110100yyzzzz,"Sy data MSB position -> MSW of Dz, clear LSW of Dz","Finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pdmsb_sy (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 overflow_bit = 0;
 #include ""integer_unconditional_update.c""
 #include ""integer_plus_dc_bit.c""
}"
"bst #imm3,Rn",10000111nnnn0iii,T -> imm of Rn,Transfers the contents of the T bit to a specified 1-bit location of the LSB 8 bits of a general register Rn. The bit number is specified by 3-bit immediate data.,"void BST (int i, int n) {
 long disp, imm;
 disp = (0x00000FFF & (long)d);
 imm = (0x00000007 & (long)i);
 if (T == 0)
 R[n] &= (~(0x00000001 << imm));
 else
 R[n] |= (0x00000001 << imm);
 PC += 2;
}
"
"bxor.b #imm3,@(disp12,Rn)",0011nnnn0iii1001 0110dddddddddddd,(imm of (disp+Rn)) ^ T -> T,"Exclusive-ORs a specified bit in memory at the address indicated by (disp + Rn) with the T bit, and stores the result in the T bit. The bit number is specified by 3-bit immediate data. With this instruction, data is read from memory as a byte unit.","void BXORM (int d, int i, int n) {
 long disp = (0x00000FFF & (long)d);
 long imm = (0x00000007 & (long)i);
 long temp = Read_8 (R[n] + disp);
 long assignbit = (0x00000001 << imm) & temp;
 if (assignbit == 0)
 {
 if (T == 0)
 T = 0;
 else
 T = 1;
 }
 else
 {
 if (T == 0)
 T = 1;
 else
 T = 0;
 }
 PC += 4;
}
"
"add Rm,Rn",0011nnnnmmmm1100,Rn + Rm -> Rn,Adds together the contents of general registers Rn and Rm and stores the result in Rn.,"void ADD (int m, int n) {
 R[n] += R[m];
 PC += 2;
}
"
"add #imm,Rn",0111nnnniiiiiiii,Rn + (sign extension)imm,"Adds together the contents of general register Rn and the immediate value and stores the result in Rn. The 8-bit immediate value is sign-extended to 32 bits, which allows it to be used for immediate subtraction or decrement operations.","void ADDI (int i, int n) {
 if ((i & 0x80) == 0)
 R[n] += (0x000000FF & (long)i);
 else
 R[n] += (0xFFFFFF00 | (long)i);
 PC += 2;
}
"
"addc Rm,Rn",0011nnnnmmmm1110,"Rn + Rm + T -> Rn, carry -> T","Adds together the contents of general registers Rn and Rm and the T bit, and stores the result in Rn. A carry resulting from the operation is reflected in the T bit. This instruction can be used to implement additions exceeding 32 bits.","void ADDC (int m, int n) {
 unsigned long tmp0, tmp1;
 tmp1 = R[n] + R[m];
 tmp0 = R[n];
 R[n] = tmp1 + T;
 if (tmp0>tmp1)
 T = 1;
 else
 T = 0;
 if (tmp1 > R[n])
 T = 1;
 PC += 2;
}
"
"addv Rm,Rn",0011nnnnmmmm1111,"Rn + Rm -> Rn, overflow -> T","Adds together the contents of general registers Rn and Rm and stores the result in Rn. If overflow occurs, the T bit is set.","void ADDV (int m, int n) {
 long dest, src, ans;
 if ((long)R[n] >= 0)
 dest = 0;
 else
 dest = 1;
 if ((long)R[m] >= 0)
 src = 0;
 else
 src = 1;
 src += dest;
 R[n] += R[m];
 if ((long)R[n] >= 0)
 ans = 0;
 else
 ans = 1;
 ans += dest;
 if (src == 0 || src == 2)
 {
 if (ans == 1)
 T = 1;
 else
 T = 0;
 }
 else
 T = 0;
 PC += 2;
}
"
"cmp/eq #imm,R0",10001000iiiiiiii,If R0 = (sign extension)imm: 1 -> T Else: 0 -> T,Compares general register R0 and the sign-extended 8-bit immediate data and sets the T bit if the values are equal. If they are not equal the T bit is cleared. The contents of R0 are not changed.,"void CMPIM (int i) {
 long imm;
 if ((i & 0x80) == 0)
 imm = (0x000000FF & (long i));
 else
 imm = (0xFFFFFF00 | (long i));
 if (R[0] == imm)
 T = 1;
 else
 T = 0;
 PC += 2;
}
"
tas.b @Rn,0100nnnn00011011,"If (Rn) = 0: 1 -> T
Else: 0 -> T
1 -> MSB of (Rn)","Reads byte data from the address specified by general register Rn, and sets the T bit to 1 if the data is 0, or clears the T bit to 0 if the data is not 0. Then, data bit 7 is set to 1, and the data is written to the address specified by Rn. During this operation, the bus is not released.",
"tst Rm,Rn",0010nnnnmmmm1000,"If Rn & Rm = 0: 1 -> T
Else: 0 -> T","ANDs the contents of general registers Rn and Rm, and sets the T bit if the result is zero. If the result is nonzero, the T bit is cleared. The contents of Rn are not changed.",
"tst #imm,R0",11001000iiiiiiii,"If R0 & (zero extend)imm = 0: 1 -> T
Else: 0 -> T","ANDs the contents of general register R0 and the zero-extended immediate value and sets the T bit if the result is zero. If the result is nonzero, the T bit is cleared. The contents of Rn are not changed.",
"tst.b #imm,@(R0,GBR)",11001100iiiiiiii,"If (R0 + GBR) & (zero extend)imm = 0: 1 -> T
Else 0: -> T","ANDs the contents of the memory byte indicated by the indirect GBR address with the zero-extended immediate value and sets the T bit if the result is zero. If the result is nonzero, the T bit is cleared. The contents of the memory byte are not changed.",
"xor Rm,Rn",0010nnnnmmmm1010,Rn ^ Rm -> Rn,XORs the contents of general registers Rn and Rm and stores the result in Rn.,
"xor #imm,R0",11001010iiiiiiii,R0 ^ (zero extend)imm -> R0,XORs the contents of general register R0 and the zero-extended immediate value and stores the result in R0.,
"xor.b #imm,@(R0,GBR)",11001110iiiiiiii,(R0 + GBR) ^ (zero extend)imm -> (R0 + GBR),XORs the contents of the memory byte indicated by the indirect GBR address with the immediate value and writes the result back to the memory byte.,
"and Rm,Rn",0010nnnnmmmm1001,Rn & Rm -> Rn,ANDs the contents of general registers Rn and Rm and stores the result in Rn.,"void AND (int m, int n) {
 R[n] &= R[m];
 PC += 2;
}"
"and #imm,R0",11001001iiiiiiii,R0 & (zero extend)imm -> R0,ANDs the contents of general register R0 and the zero-extended immediate value and stores the result in R0.,"void ANDI (int i) {
 R[0] &= (0x000000FF & (long)i);
 PC += 2;
}"
"and.b #imm,@(R0,GBR)",11001101iiiiiiii,(R0 + GBR) & (zero extend)imm -> (R0 + GBR),ANDs the contents of the memory byte indicated by the indirect GBR address with the immediate value and writes the result back to the memory byte.,"void ANDM (long i) {
 long temp = Read_8 (GBR + R[0]);
 temp &= 0x000000FF & (long)i;
 Write_8 (GBR + R[0], temp);
 PC += 2;
}"
"not Rm,Rn",0110nnnnmmmm0111,~Rm -> Rn,"Finds the one's complement of the contents of general register Rm and stores the result in Rn. That is, it inverts the Rm bits and stores the result in Rn.","void NOT (int m, int n) {
 R[n] = ~R[m];
 PC += 2;
}"
"or Rm,Rn",0010nnnnmmmm1011,Rn | Rm -> Rn,ORs the contents of general registers Rn and Rm and stores the result in Rn.,"void OR (int m, int n) {
 R[n] |= R[m];
 PC += 2;
}"
"or #imm,R0",11001011iiiiiiii,R0 | (zero extend)imm -> R0,ORs the contents of general register R0 and the zero-extended immediate value and stores the result in R0.,"void ORI (int i) {
 R[0] |= (0x000000FF & (long)i);
 PC += 2;
}"
"or.b #imm,@(R0,GBR)",11001111iiiiiiii,(R0 + GBR) | (zero extend)imm -> (R0 + GBR),ORs the contents of the memory byte indicated by the indirect GBR address with the immediate value and writes the result back to the memory byte.,"void ORM (int i) {
 long temp = Read_8 (GBR + R[0]);
 temp |= (0x000000FF & (long)i);
 Write_8 (GBR + R[0], temp);
 PC += 2;
}"
dct pclr Dz,111110********** 100011100000zzzz,"If DC = 1: 0x00000000 -> Dz
Else: nop","Conditionally clears the Dz operand. The instruction is executed when the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pclr_dct (void)
{
 if (DC == 1)
 DSP_REG[ex2_dz_no] = 0x0;
}"
dcf pclr Dz,111110********** 100011110000zzzz,"If DC = 0: 0x00000000 -> Dz
Else: nop","Conditionally clears the Dz operand. The instruction is executed when the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pclr_dcf (void)
{
 if (DC == 0)
 DSP_REG[ex2_dz_no] = 0x0;
}"
"pcmp Sx,Sy",111110********** 10000100xxyy0000,Sx - Sy,"Subtracts the contents of the Sy operand from the Sx operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pcmp (void)
{
 switch (EX2_SX)
 {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
negative_bit = DSP_ALU_DSTG_BIT7;
 zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_minus_dc_bit.c""
}"
"dcf pinc Sx,Dz",111110********** 10011011xx00zzzz,"If DC = 0: MSW of Sx + 1 -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pinc_sx_dcf (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 if (DC == 0) {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 }
}"
"dcf psub Sx,Sy,Dz",111110********** 10100011xxyyzzzz,If DC = 0: Sx - Sy -> Dz Else: nop,"Conditionally subtracts the contents of the Sy operand from the Sx operand and stores the result in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void psub_dct (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG[ex2_dz_no] = DSP_ALU_DST;
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"dcf padd Sx,Sy,Dz",111110********** 10110011xxyyzzzz,If DC = 0: Sx + Sy -> Dz Else: nop,"Conditionally adds the contents of the Sx and Sy operands and stores the result in the Dz operand. The instruction is executed of the DC bit is set to 0. Otherwise no operation is performed. The DC, N, Z, V, and GT bits are not updated.","void padd_dct (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1: DSP_ALU_SRC2 = Y1;
 break;
 case 0x2: DSP_ALU_SRC2 = M0;
 break;
 case 0x3: DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG [ex2_dz_no] = DSP_ALU_DST;
 if(ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7) A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no==1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"muls.w Rm,Rn",0010nnnnmmmm1111,"Signed, Rn * Rm -> MACL
16 * 16 -> 32 bits","Performs 16-bit multiplication of the contents of general registers Rn and Rm, and stores the 32-bit result in the MACL register. The multiplication is performed as a signed arithmetic operation. The contents of MACH are not changed.","void MULS (int m, int n) {
 MACL = ((long)(short)R[n] * (long)(short)R[m]);
 PC += 2;
}"
"mulu.w Rm,Rn",0010nnnnmmmm1110,"Unsigned, Rn * Rm -> MACL
16 * 16 -> 32 bits","Performs 16-bit multiplication of the contents of general registers Rn and Rm, and stores the 32-bit result in the MACL register. The multiplication is performed as an unsigned arithmetic operation. The contents of MACH are not changed.","void MULU (int m, int n) {
 MACL = ((unsigned long)(unsigned short)R[n]* (unsigned long)(unsigned short)R[m];
 PC += 2;
}"
"neg Rm,Rn",0110nnnnmmmm1011,0 - Rm -> Rn,"Finds the two's complement of the contents of general register Rm and stores the result in Rn. That is, it subtracts Rm from 0 and stores the result in Rn.","void NEG (int m, int n) {
 R[n] = 0 - R[m];
 PC += 2;
}"
"negc Rm,Rn",0110nnnnmmmm1010,"0 - Rm - T -> Rn, borrow -> T",Subtracts the contents of general register Rm and the T bit from 0 and stores the result in Rn. A borrow resulting from the operation is reflected in the T bit. This instruction can be used for sign inversion of a value exceeding 32 bits.,"void NEGC (int m, int n) {
 unsigned long temp;
 temp = 0 - R[m];
 R[n] = temp - T;
 if (0 < temp)
 T = 1;
 else
 T = 0;
 if (temp < R[n])
 T = 1;
 PC += 2;
}"
"sub Rm,Rn",0011nnnnmmmm1000,Rn - Rm -> Rn,"Subtracts the contents of general register Rm from the contents of general register Rn and stores the result in Rn. For immediate data subtraction, ADD #imm,Rn should be used.","void SUB (int m, int n) {
 R[n] -= R[m];
 PC += 2;
}"
"subc Rm,Rn",0011nnnnmmmm1010,"Rn - Rm - T -> Rn, borrow -> T","Subtracts the contents of general register Rm and the T bit from the contents of general register Rn, and stores the result in Rn. A borrow resulting from the operation is reflected in the T bit. This instruction is used for subtractions exceeding 32 bits.","void SUBC (int m, int n) {
 unsigned long tmp0, tmp1;
 tmp1 = R[n] - R[m];
 tmp0 = R[n];
 R[n] = tmp1 - T;
 if (tmp0 < tmp1)
 T = 1;
 else
 T = 0;
 if (tmp1 < R[n])
 T = 1;
 PC += 2;
}"
"subv Rm,Rn",0011nnnnmmmm1011,"Rn - Rm -> Rn, underflow -> T","Subtracts the contents of general register Rm from the contents of general register Rn, and stores the result in Rn. If underflow occurs, the T bit is set.","void SUBV (int m, int n) {
 long dest, src, ans;
 if ((long)R[n] >= 0)
 dest = 0;
 else
 dest = 1;
 if ((long)R[m] >= 0)
 src = 0;
 else
 src = 1;
 src += dest;
 R[n] -= R[m];
 if ((long)R[n] >= 0)
 ans = 0;
 else
 ans = 1;
 ans += dest;
 if (src == 1)
 {
 if (ans == 1)
 T = 1;
 else
 T = 0;
 }
 else
 T = 0;
 PC += 2;
}"
"prnd Sy,Dz",111110********** 1011100000yyzzzz,"Sy + 0x00008000 -> Dz, clear LSW of Dz","Does rounding. Adds the immediate data 0x00008000 to the contents of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of Dz with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void prnd_sy (void) { switch (EX2_SY) { case 0x0: DSP_ALU_SRC1 = Y0; break; case 0x1: DSP_ALU_SRC1 = Y1; break; case 0x2: DSP_ALU_SRC1 = M0; break; case 0x3: DSP_ALU_SRC1 = M1; break; } if (DSP_ALU_SRC1_MSB) DSP_ALU_SRC1G = 0xFF; else DSP_ALU_SRC1G = 0x0; DSP_ALU_DST = (DSP_ALU_SRC1 + DSP_ALU_SRC2) & MASKFFFF0000; carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB) | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB); DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit; overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV); #include ""fixed_pt_overflow_protection.c"" #include ""fixed_pt_unconditional_update.c"" #include ""fixed_pt_plus_dc_bit.c"" }"
"mov.l @-Rm,R0",0100mmmm11101011,"Rm-4 -> Rm, (Rm) -> R0",Transfers the source operand to the destination.,"void MOVRSLM (int m) {
 R[m] -= 4;
 R[0] = Read_32 (R[m]);
 PC += 2;
}"
"mov.b R0,@Rn+",0100nnnn10001011,"R0 -> (Rn), Rn+1 -> Rn",Transfers the source operand to the destination.,"void MOVRSBP (int n) {
 Write_8 (R[n], R[0]);
 R[n] += 1;
 PC += 2;
}"
"mov.w R0,@Rn+",0100nnnn10011011,"R0 -> (Rn), Rn+2 -> Rn",Transfers the source operand to the destination.,"void MOVRSWP (int n) {
 Write_16 (R[n], R[0]);
 R[n] += 2;
 PC += 2;
}"
"mov.l R0,@Rn+",0100nnnn10101011,"R0 -> (Rn), Rn+4 -> Rn",Transfers the source operand to the destination.,"void MOVRSLP (int n) {
 Write_32 (R[n], R[0]);
 R[n] += 4;
 PC += 2;
}"
"mov.b @(disp,Rm),R0",10000100mmmmdddd,(disp + Rm) -> sign extension -> R0,"Transfers the source operand to the destination. The 4-bit displacement is only zero-extended, so a range up to +15 bytes can be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. The loaded data is sign-extended to 32 bit before being stored in the destination register.","void MOVBL4 (int m, int d) {
 long disp = (0x0000000F & (long)d);
 R[0] = Read_8 (R[m] + disp);
 if ((R[0] & 0x80) == 0)
 R[0] &= 0x000000FF;
 else
 R[0] |= 0xFFFFFF00;
 PC += 2;
}"
"mov.b @(disp12,Rm),Rn",0011nnnnmmmm0001 0100dddddddddddd,(disp + Rm) -> sign extension -> Rn,Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register.,"void MOVBL12 (int d, int m, int n) {
 long disp = (0x00000FFF & (long)d);
 R[n] = Read_8 (R[m] + disp);
 if ((R[n] & 0x80) == 0)
 R[n] &= 0x000000FF;
 else
 R[n] |= 0xFFFFFF00;
 PC += 4;
}"
"movu.b @(disp12,Rm),Rn",0011nnnnmmmm0001 1000dddddddddddd,(disp + Rm) -> zero extension -> Rn,"Transfers a source operand to a destination, performing unsigned data transfer. This instruction is ideal for data access in a structure or the stack. The loaded data is zero-extended to 32 bit before being stored in the destination register.","void MOVBUL12 (int d, int m, int n) {
 long disp = (0x00000FFF & (long)d);
 R[n] = Read_8 (R[m] + disp);
 R[n] &= 0x000000FF;
 PC += 4;
}"
"fdiv FRm,FRn",1111nnnnmmmm0011,FRn / FRm -> FRn,"Arithmetically divides the single-precision floating-point number in FRn by the single-precision floating-point number in FRm, and stores the result in FRn.","void FDIV (int m, int n) {
 PC += 2;
 clear_cause ();
 if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
 invalid (n);
 else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
 qnan (n);
 else
 switch (data_type_of (m))
 {
 case NORM:
 switch (data_type_of (n))
 {
 case PINF:
 case NINF:
 inf (n, sign_of (m) ^ sign_of (n));
 break;
 case PZERO:
 case NZERO:
 zero (n, sign_of (m) ^ sign_of (n));
 break;
 case DENORM:
 set_E ();
 break;
 default:
 normal_fdiv_single (m, n);
 break;
 }
 break;
 case PZERO:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 invalid (n);
 break;
 case PINF:
 case NINF:
 break;
 default:
 dz (n, sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 case NZERO:
 switch (data_type_of (n))
 {
 case PZERO:
 case NZERO:
 invalid (n);
 break;
 case PINF:
 inf (n, 1);
 break;
 case NINF:
 inf (n, 0);
 break;
 default:
 dz (FR[n], sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 case DENORM:
 set_E ();
 break;
 case PINF:
 case NINF:
 switch (data_type_of (n))
 {
 case DENORM:
 set_E ();
 break;
 case PINF:
 case NINF:
 invalid (n);
 break;
 default:
 zero (n, sign_of (m) ^ sign_of (n));
 break;
 }
 break;
 }
}
void normal_fdiv_single (int m, int n) {
 union
 {
 float f;
 int l;
 } dstf, tmpf;
 union
 {
 double d;
 int l[2];
 } tmpd;
 tmpf.f = FR[n]; // save destination value
 dstf.f /= FR[m]; // round toward nearest or even
 tmpd.d = dstf.f; // convert single to double
 tmpd.d *= FR[m];
 if (tmpf.f != tmpd.d)
 set_I ();
 if (tmpf.f < tmpd.d && FPSCR_RM == 1)
 dstf.l -= 1; // round toward zero
 check_single_exception (&FR[n], dstf.f);
}"
rts,0000000000001011,"PR -> PC
Delayed branch",Returns from a subroutine procedure by restoring the PC from PR. Processing continues from the address indicated by the restored PC value. This instruction can be used to return from a subroutine procedure called by a BSR or JSR instruction to the source of the call.,"void RTS (void)
{
 unsigned int temp;
 temp = PC;
 PC = PR;
 Delay_Slot (temp + 2);
}"
rts/n,0000000001101011,PR -> PC,"Performs a return from a subroutine procedure. That is, the PC is restored from PR, and processing is resumed from the address indicated by the PC. This instruction enables a return to be made from a subroutine procedure called by a BSR or JSR instruction to the origin of the call.","void RTSN (void)
{
 PC = PR;
}"
rtv/n Rm,0000mmmm01111011,"Rm -> R0, PR -> PC","Performs a return from a subroutine procedure after a transfer from specified general register Rm to R0. That is, after the Rm value is stored in R0, the PC is restored from PR, and processing is resumed from the address indicated by the PC. This instruction enables a return to be made from a subroutine procedure called by a BSR or JSR instruction to the origin of the call.","void RTVN (int m)
{
 R[0] = R[m];
 PC = PR;
}"
clrmac,0000000000101000,"0 -> MACH, 0 -> MACL",Clears the MACH and MACL registers.,"void CLRMAC (void)
{
 MACH = 0;
 MACL = 0;
 PC += 2;
}"
clrs,0000000001001000,0 -> S,Clears the S bit to 0.,"void CLRS (void)
{
 S = 0;
 PC += 2;
}"
clrt,0000000000001000,0 -> T,Clears the T bit.,"void CLRT (void)
{
 T = 0;
 PC += 2;
}"
icbi @Rn,0000nnnn11100011,Invalidate instruction cache block indicated by logical address,"Accesses the instruction cache at the effective address indicated by the contents of Rn. When the cache is hit, the corresponding cache block is invalidated (the V bit is cleared to 0). At this time, write-back is not performed. No operation is performed in the case of a cache miss or access to a non-cache area.","void ICBI (int n)
{
 invalidate_instruction_cache_block (R[n]);
 PC += 2;
}"
"movs.l @As,Ds",111101AADDDD0110,(As) -> Ds,"Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.l @As+,Ds",111101AADDDD1010,"(As) -> Ds, As+4 -> As","Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.l @As+Is,Ds",111101AADDDD1110,"(As) -> Ds, As+Is -> As","Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits.",
"movs.l Ds,@-As",111101AADDDD0011,"As-4 -> As, Ds -> (As)",Transfers the source operand data to the destination. The transferred data is a longword.,
"movs.l Ds,@As",111101AADDDD0111,Ds -> (As),Transfers the source operand data to the destination. The transferred data is a longword.,
"fadd DRm,DRn",1111nnn0mmm00000,DRn + DRm -> DRn,"Arithmetically adds the two double-precision floating-point numbers in DRn and DRm, and stores the result in DRn.","void FADD (int m, int n) {
 PC += 2;
 clear_cause ();
 if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
 invalid (n);
 else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
 qnan (n);
 else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
 set_E ();
 else
 switch (data_type_of (m))
 {
 case NORM:
 switch (data_type_of (n))
 {
 case NORM:
 normal_faddsub (m, n, ADD);
 break;
 case PZERO:
 case NZERO:
 register_copy (m, n);
 break;
 default:
 break;
 }
 break;
 case PZERO:
 switch (data_type_of (n))
 {
 case NZERO:
 zero (n, 0);
 break;
 default:
 break;
 }
 break;
 case NZERO:
 break;
 case PINF:
 switch (data_type_of (n))
 {
 case NINF:
 invalid (n);
 break;
 default:
 inf (n, 0);
 break;
 }
 break;
 case NINF:
 switch (data_type_of (n))
 {
 case PINF:
 invalid (n);
 break;
 default:
 inf (n, 1);
 break;
 }
 break;
 }
}"
fsqrt DRn,1111nnn001101101,sqrt (DRn) -> DRn,"Finds the arithmetical square root of the double-precision floating-point number in DRn, and stores the result in DRn. When FPSCR.enable.I is set, an FPU exception trap is generated regardless of whether or not an exception has occurred. When an exception occurs, correct exception information is reflected in FPSCR.cause and FPSCR.flag and DRn is not updated. Appropriate processing should therefore be performed by software.","void FSQRT (int n) {
 PC += 2;
 clear_cause ();
 switch (data_type_of (n)) {
 case NORM:
 if (sign_of (n) == 0)
 normal_fsqrt_double (n);
 else
 invalid (n);
 break;
 case DENORM:
 if (sign_of (n) == 0)
 set_E ();
 else
 invalid (n);
 break;
 case PZERO:
 case NZERO:
 case PINF:
 break;
 case NINF:
 invalid (n);
 break;
 case qNAN:
 qnan (n);
 break;
 case sNAN:
 invalid (n);
 break;
 }
}
void normal_fsqrt_double (int n) {
 union {
 double d;
 int l[2];
 } dstd, tmpd;
 union {
 int double x;
 int l[4];
 } tmpx;
 tmpd.d = DR[n >> 1]; // save destination value
 dstd.d = sqrt (DR[n >> 1]); // round toward nearest or even
 tmpx.x = dstd.d; // convert double to int double
 tmpx.x *= dstd.d;
 if (tmpd.d != tmpx.x)
 set_I ();
 if (tmpd.d < tmpx.x && FPSCR_RM == 1)
 {
 dstd.l[1] -= 1; // round toward zero
 if (dstd.l[1] == 0xFFFFFFFF)
 dstd.l[0] -= 1;
 }
 if (FPSCR & ENABLE_I)
 fpu_exception_trap();
 else
 DR[n >> 1] = dstd.d;
}"
fsqrt FRn,1111nnnn01101101,sqrt (FRn) -> FRn,"Finds the arithmetical square root of the single-precision floating-point number in FRn, and stores the result in FRn. When FPSCR.enable.I is set, an FPU exception trap is generated regardless of whether or not an exception has occurred. When an exception occurs, correct exception information is reflected in FPSCR.cause and FPSCR.flag and FRn is not updated. Appropriate processing should therefore be performed by software.","void FSQRT (int n) {
 PC += 2;
 clear_cause ();
 switch (data_type_of (n)) {
 case NORM:
 if (sign_of (n) == 0)
 normal_fsqrt_single (n);
 else
 invalid (n);
 break;
 case DENORM:
 if (sign_of (n) == 0)
 set_E ();
 else
 invalid (n);
 break;
 case PZERO:
 case NZERO:
 case PINF:
 break;
 case NINF:
 invalid (n);
 break;
 case qNAN:
 qnan (n);
 break;
 case sNAN:
 invalid (n);
 break;
 }
}
void normal_fsqrt_single (int n) {
 union {
 float f;
 int l;
 } dstf, tmpf;
 union {
 double d;
 int l[2];
 } tmpd;
 tmpf.f = FR[n]; // save destination value
 dstf.f = sqrt (FR[n]); // round toward nearest or even
 tmpd.d = dstf.f; // convert single to double
 tmpd.d *= dstf.f;
 if (tmpf.f != tmpd.d)
 set_I ();
 if (tmpf.f < tmpd.d && FPSCR_RM == 1)
 dstf.l -= 1; // round toward zero
 if (FPSCR & ENABLE_I)
 fpu_exception_trap ();
 else
 FR[n] = dstf.f;
}"
"pcopy Sy,Dz",111110********** 1111100100yyzzzz,Sy -> Dz,"Stores the Sy operand in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits are also updated.","void pcopy_sy (void) {
 DSP_ALU_SRC1 = 0;
 DSP_ALU_SRC1G = 0;
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_plus_dc_bit.c""
}"
"dcf pdmsb Sy,Dz",111110********** 1011111100yyzzzz,"If DC = 0: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pdmsb_sy_dcf (void) {
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"lds.l @Rm+,A0",0100mmmm01110110,"(Rm) -> A0, Rm+4 -> Rm",Stores the source operand into the DSP register A0. The MSB of the data is copied into A0G.,"void LDSMA0 (int m) {
 A0 = Read_32 (R[m]);
 if ((A0 & 0x80000000) == 0)
 A0G = 0x00;
 else
 A0G = 0xFF;
 R[m] += 4;
 PC += 2;
}"
"lds Rm,X0",0100mmmm10001010,Rm -> X0,Stores the source operand into the DSP register X0.,"void LDSX0 (int m) {
 X0 = R[m];
 PC += 2;
}"
"lds.l @Rm+,X0",0100nnnn10000110,"(Rm) -> X0, Rm+4 -> Rm",Stores the source operand into the DSP register X0.,"void LDSMX0 (int m) {
 X0 = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"lds Rm,X1",0100mmmm10011010,Rm -> X1,Stores the source operand into the DSP register X1.,"void LDSX1 (int m) {
 X1 = R[m];
 PC += 2;
}"
"lds.l @Rm+,X1",0100nnnn10010110,"(Rm) -> X1, Rm+4 -> Rm",Stores the source operand into the DSP register X1.,"void LDSMX1 (int m) {
 X1 = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"lds Rm,Y0",0100mmmm10101010,Rm -> Y0,Stores the source operand into the DSP register Y0.,"void LDSY0 (int m) {
 Y0 = R[m];
 PC += 2;
}"
"lds.l @Rm+,Y0",0100nnnn10100110,"(Rm) -> Y0, Rm+4 -> Rm",Stores the source operand into the DSP register Y0.,"void LDSMY0 (int m) {
 Y0 = Read_32 (R[m]);
 R[m] += 4;
 PC += 2;
}"
"float FPUL,DRn",1111nnn000101101,(double)FPUL -> DRn,"Taking the contents of FPUL as a 32-bit integer, converts this integer to a double-precision floating-point number and stores the result in DRn.","void FLOAT_double (int n) {
 union
 {
 double d;
 int l[2];
 } tmp;
 PC += 2;
 clear_cause ();
 DR[n >> 1] = FPUL; // convert from integer to double
}
"
"dcf pdec Sy,Dz",111110********** 1010101100yyzzzz,"If DC = 0: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop","Conditionally subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pdec_sy_dcf (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"dcf pdec Sx,Dz",111110********** 10001011xx00zzzz,"If DC = 0: MSW of Sx - 1 -> MSW of DZ, clear LSW of Dz
Else: nop","Conditionally subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pdec_sx_dcf (void)
{
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SX)
 {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"stc.l RE,@-Rn",0100nnnn01110011,"Rn-4 -> Rn, RE -> (Rn)",Stores control register RE in the destination.,"void STCMRE (int n) {
 R[n] -= 4;
 Write_32 (R[n], RE);
 PC += 2;
}"
"stc RS,Rn",0000nnnn01100010,RS -> Rn,Stores control register RS in the destination.,"void STCRS (int n) {
 R[n] = RS;
 PC += 2;
}"
"stc.l RS,@-Rn",0100nnnn01100011,"Rn-4 -> Rn, RS -> (Rn)",Stores control register RS in the destination.,"void STCMRS (int n) {
 R[n] -= 4;
 Write_32 (R[n], RS);
 PC += 2;
}"
"stc SGR,Rn",0000nnnn00111010,SGR -> Rn,Stores control register SGR in the destination.,"void STCSGR (int n) {
 R[n] = SGR;
 PC += 2;
}"
"stc.l SGR,@-Rn",0100nnnn00110010,"Rn-4 -> Rn, SGR -> (Rn)",Stores control register SGR in the destination.,"void STCMSGR (int n) {
 R[n] -= 4;
 Write_32 (R[n], SGR);
 PC += 2;
}"
"stc SSR,Rn",0000nnnn00110010,SSR -> Rn,Stores control register SSR in the destination.,"void STCSSR (int n) {
 R[n] = SSR;
 PC += 2;
}"
"stc.l SSR,@-Rn",0100nnnn00110011,"Rn-4 -> Rn, SSR -> (Rn)",Stores control register SSR in the destination.,"void STCMSSR (int n) {
 R[n] -= 4;
 Write_32 (R[n], SSR);
 PC += 2;
}"
"dct pdec Sy,Dz",111110********** 1010101000yyzzzz,"If DC = 1: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop","Conditionally subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pdec_sy_dct (void) {
 DSP_ALU_SRC2 = 0x1;
 DSP_ALU_SRC2G = 0x0;
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC1 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = M1;
 break;
 }
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
 borrow_bit = ! carry_bit;
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"fcmp/eq DRm,DRn",1111nnn0mmm00100,If DRn = DRm: 1 -> T Else: 0 -> T,"Arithmetically compares the two double-precision floating-point numbers in DRn and DRm, and stores 1 in the T bit if they are equal, or 0 otherwise.","void FCMP_EQ (int m, int n) { PC += 2; clear_cause (); if (fcmp_chk_double (m, n) == INVALID) fcmp_invalid (); else if (fcmp_chk_double (m, n) == EQ) T = 1; else T = 0; }"
"fcmp/gt DRm,DRn",1111nnn0mmm00101,If DRn > DRm: 1 -> T Else: 0 -> T,"Arithmetically compares the two double-precision floating-point numbers in DRn and DRm, and stores 1 in the T bit if DRn > DRm, or 0 otherwise.","void FCMP_GT (int m, int n) { PC += 2; clear_cause (); if (fcmp_chk_double (m, n) == INVALID || fcmp_chk_double (m, n) == UO) fcmp_invalid (); else if (fcmp_chk_double (m, n) == GT) T = 1; else T = 0; }"
"float FPUL,DRn",1111nnn000101101,(double)FPUL -> DRn,"Taking the contents of FPUL as a 32-bit integer, converts this integer to a double-precision floating-point number and stores the result in DRn.",void FLOAT_double (int n) { union { double d; int l[2]; } tmp; PC += 2; clear_cause (); DR[n >> 1] = FPUL; }
"ftrc DRm,FPUL",1111mmm000111101,(long)DRm -> FPUL,"Converts the double-precision floating-point number in DRm to a 32-bit integer, and stores the result in FPUL.","void FTRC_double (int m) { PC += 2; clear_cause (); switch (ftrc_double_type_of (m)) { case NORM: FPUL = DR[m >> 1]; break; case PINF: ftrc_invalid (0, &FPUL); break; case NINF: ftrc_invalid (1, &FPUL); break; } }"
"fcnvds DRm,FPUL",1111mmm010111101,double_to_float (DRm) -> FPUL,"Converts the double-precision floating-point number in DRm to a single-precision floating-point number, and stores the result in FPUL.","void FCNVDS (int m) { if (FPSCR_PR != 1) undefined_operation (); else { PC += 2; clear_cause (); switch (data_type_of (m)) { case NORM: case PZERO: case NZERO: normal_fcnvds (m, &FPUL); break; case DENORM: set_E (); case PINF: FPUL = 0x7F800000; break; case NINF: FPUL = 0xFF800000; break; case qNaN: FPUL = 0x7FBFFFFF; break; case sNaN: set_V (); if ((FPSCR & ENABLE_V) == 0) FPUL = 0x7FBFFFFF; else fpu_exception_trap (); break; } } }"
"paddc Sx,Sy,Dz",111110********** 10110000xxyyzzzz,Sx + Sy + DC -> Dz,"Adds the contents of the Sx and Sy operands to the DC bit and stores the result in the Dz operand. The DC bit of the DSR register is updated as the carry flag. The N, Z, V, and GT bits of the DSR register are also updated.","void paddc (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 switch (EX2_SY) {
 case 0x0:
 DSP_ALU_SRC2 = Y0;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1;
 break;
 }
 if (DSP_ALU_SRC2_MSB)
 DSP_ALU_SRC2G = 0xFF;
 else
 DSP_ALU_SRC2G = 0x0;
 DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2 + DSPDCBIT;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""fixed_pt_overflow_protection.c""
 #include ""fixed_pt_unconditional_update.c""
 #include ""fixed_pt_dc_always_carry.c""
}"
"dcf pshl Sx,Sy,Dz",111110********** 10000011xxyyzzzz,"If DC = 0 & Sy >= 0: Sx << Sy -> Dz, clear LSW of Dz
If DC = 0 & Sy < 0: Sx >> Sy -> Dz, clear LSW of Dz
If DC = 1: nop","Conditionally logically shifts the top word contents of the Sx operand, stores
the result in the top word of the Dz operand, and clears the bottom word of the
Dz operand with zeros. When Dz is a register that has guard bits, the guard bits
are also zeroed. The amount of the shift is specified by the Sy operand. When
the shift amount is positive, it shifts left. When the shift amount is negative,
it shifts right.
The instruction is executed if the DC bit is set to 0.
The DC, N, Z, V, and GT bits are not updated.","void pshl_dcf (void)
{
 switch (EX2_SX)
 {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 break;
 }
 switch (EX2_SY)
 {
 case 0x0:
 DSP_ALU_SRC2 = Y0 & MASK003F0000;
 break;
 case 0x1:
 DSP_ALU_SRC2 = Y1 & MASK003F0000;
 break;
 case 0x2:
 DSP_ALU_SRC2 = M0 & MASK003F0000;
 break;
 case 0x3:
 DSP_ALU_SRC2 = M1 & MASK003F0000;
 break;
 }
 if ((DSP_ALU_SRC2_HW & MASK0020) == 0)
 {
 // Left Shift 0 <= cnt <= 16
 char cnt = DSP_ALU_SRC2_HW & MASK001F;
 if (cnt > 16)
 {
 printf (""\nPSHL Sx,Sy,Dz Error! Shift %2X exceed range.\n"", cnt);
 exit ();
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW << cnt--;
 carry_bit = ((DSP_ALU_SRC1_HW << cnt) & MASK8000) == 0x8000;
 }
 else
 {
 // Right Shift 0 < cnt <= 16
 char cnt = (~DSP_ALU_SRC2_HW & MASK000F) + 1;
 if (cnt > 16)
 {
 printf (""\nPSHL Sx,Sy,Dz Error! Shift -%2X exceed range.\n"", cnt);
 exit ();
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW >> cnt--;
 carry_bit = ((DSP_ALU_SRC1_HW >> cnt) & MASK0001) == 0x1;
 }
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 A0G = 0x0; // clear Guard bits
 else if (ex2_dz_no == 1)
 A1G = 0x0;
 }
}"
"dcf pinc Sx,Dz",111110********** 10011011xx00zzzz,"If DC = 0: MSW of Sx + 1 -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pinc_sx_dcf (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"pdmsb Sx,Dz",111110********** 10011101xx00zzzz,"Sx data MSB position -> MSW of Dz, clear LSW of Dz","Finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated.","void pdmsb_sx (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 overflow_bit = 0;
 #include ""integer_unconditional_update.c""
 #include ""integer_plus_dc_bit.c""
}"
"dct pinc Sx,Dz",111110********** 10011010xx00zzzz,"If DC = 1: MSW of Sx + 1 -> MSW of Dz, clear LSW of Dz
Else: nop","Conditionally adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated.","void pinc_sx_dct (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
 carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
 | (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
 DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
 overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
 #include ""integer_overflow_protection.c""
 if (DC == 1)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"sts.l MACH,@-Rn",0100nnnn00000010,"Rn-4 -> Rn, MACH -> (Rn)",Stores system register MACH in the destination.,"void STSMMACH (int n) {
 R[n] -= 4;
 #if SH1
 if ((MACH & 0x00000200) == 0)
 Write_32 (R[n], MACH & 0x000003FF);
 else
 Write_32 (R[n], MACH | 0xFFFFFC00)
 #else
 Write_32 (R[n], MACH);
 #endif
 PC += 2;
}"
"sts MACL,Rn",0000nnnn00011010,MACL -> Rn,Stores system register MACL in the destination.,"void STSMACL (int n) {
 R[n] = MACL;
 PC += 2;
}"
"sts.l MACL,@-Rn",0100nnnn00010010,"Rn-4 -> Rn, MACL -> (Rn)",Stores system register MACL in the destination.,"void STSMMACL (int n) {
 R[n] -= 4;
 Write_32 (R[n], MACL);
 PC += 2;
}"
"sts PR,Rn",0000nnnn00101010,PR -> Rn,Stores system register PR in the destination.,"void STSPR (int n) {
 R[n] = PR;
 PC += 2;
}"
"sts.l PR,@-Rn",0100nnnn00100010,"Rn-4 -> Rn, PR -> (Rn)",Stores system register PR in the destination.,"void STSMPR (int n) {
 R[n] -= 4;
 Write_32 (R[n], PR);
 PC += 2;
}"
"sts DSR,Rn",0000nnnn01101010,DSR -> Rn,Stores DSP register DSR in the destination.,"void STSDSR (int n) {
 R[n] = DSR;
 PC += 2;
}"
"sts.l DSR,@-Rn",0100nnnn01100010,"Rn-4 -> Rn, DSR -> (Rn)",Stores DSP register DSR in the destination.,"void STSMDSR (int n) {
 R[n] -= 4;
 Write_32 (R[n], DSR);
 PC += 2;
}"
"dcf pdmsb Sx,Dz",111110********** 10011111xx00zzzz,"If DC = 0: Sx data MSB position -> MSW of Dz, clear LSW of Dz Else: nop","Conditionally finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated.","void pdmsb_sx_dcf (void) {
 switch (EX2_SX) {
 case 0x0:
 DSP_ALU_SRC1 = X0;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x1:
 DSP_ALU_SRC1 = X1;
 if (DSP_ALU_SRC1_MSB)
 DSP_ALU_SRC1G = 0xFF;
 else
 DSP_ALU_SRC1G = 0x0;
 break;
 case 0x2:
 DSP_ALU_SRC1 = A0;
 DSP_ALU_SRC1G = A0G;
 break;
 case 0x3:
 DSP_ALU_SRC1 = A1;
 DSP_ALU_SRC1G = A1G;
 break;
 }
 short int i;
 unsigned char msb, src1g;
 unsigned long src1 = DSP_ALU_SRC1;
 msb = DSP_ALU_SRC1G_BIT7;
 src1g = (DSP_ALU_SRC1G_LSB8 << 1);
 for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
 src1g <<= 1;
 if (i == 31)
 for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
 src1 <<= 1;
 DSP_ALU_DST = 0x0;
 DSP_ALU_DST_HW = (short int)(30 - i);
 if (DSP_ALU_DST_MSB)
 DSP_ALU_DSTG_LSB8 = 0xFF;
 else
 DSP_ALU_DSTG_LSB8 = 0x0;
 carry_bit = 0;
 if (DC == 0)
 {
 DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
 DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
 if (ex2_dz_no == 0)
 {
 A0G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A0G = A0G | MASKFFFFFF00;
 }
 else if (ex2_dz_no == 1)
 {
 A1G = DSP_ALU_DSTG & MASK000000FF;
 if (DSP_ALU_DSTG_BIT7)
 A1G = A1G | MASKFFFFFF00;
 }
 }
}"
"ftrv XMTRX,FVn",1111nn0111111101,"transform_vector (XMTRX, FVn) -> FVn","Takes the contents of floating-point registers XF0 to XF15 indicated by XMTRX as a 4-row × 4-column matrix, takes the contents of floating-point registers FR[n] to FR[n + 3] indicated by FVn as a 4-dimensional vector, multiplies the array by the vector, and stores the results in FV[n].","void FTRV (int n) {
 if (FPSCR_PR != 0)
 undefined_operation ();
 else
 {
 float saved_vec[4];
 float result_vec[4];
 int saved_fpscr;
 int dst;
 PC += 2;
 clear_cause ();
 saved_fpscr = FPSCR;
 FPSCR &= ~ENABLE_VOUI; // mask VOUI enable
 dst = 12 - n; // select other vector than FVn
 for (int i = 0; i < 4; i++)
 saved_vec[i] = FR[dst+i];
 for (int i = 0; i < 4; i++)
 {
 for (int j = 0; j < 4; j++)
 FR[dst+j] = XF[i+4j];
 fipr (n, dst);
 saved_fpscr |= FPSCR & (CAUSE | FLAG);
 result_vec[i] = FR[dst+3];
 }
 for (int i = 0; i < 4; i++)
 FR[dst+i] = saved_vec[i];
 FPSCR = saved_fpscr;
 if (FPSCR & ENABLE_VOUI)
 fpu_exception_trap();
 else
 for (int i = 0; i < 4; i++)
 FR[n+i] = result_vec[i];
 }
}"
fsrra FRn,1111nnnn01111101,1.0 / sqrt (FRn) -> FRn,"Takes the approximate inverse of the arithmetic square root (absolute error is within ±2^-21) of the single-precision floating-point in FRn and writes the result to FRn. Since the this instruction operates by approximation, an imprecision exception is required when the input is a normalized value. In other cases, the instruction does not require an imprecision exception.","void FSRRA (int n) {
 if (FPSCR_PR != 0)
 undefined_operation ();
 else
 {
 PC += 2;
 clear_cause();
 switch (data_type_of (n))
 {
 case NORM:
 if (sign_of (n) == 0)
 {
 set_I ();
 FR[n] = 1 / sqrt (FR[n]);
 }
 else
 invalid (n);
 break;
 case DENORM:
 if (sign_of (n) == 0)
 fpu_error ();
 else
 invalid (n);
 break;
 case PZERO:
 case NZERO:
 dz (n, sign_of (n));
 break;
 case PINF:
 FR[n] = 0;
 break;
 case NINF:
 invalid (n);
 break;
 case qNAN:
 qnan (n);
 break;
 case sNAN:
 invalid (n);
 break;
 }
 }
}"
"fsca FPUL,DRn",1111nnn011111101,"sin (FPUL) -> FRn
cos (FPUL) -> FR[n+1]","Calculates the sine and cosine approximations of FPUL (absolute error is within ±2^-21) as single-precision floating point values, and places the values of the sine and cosine in FRn and FR[n + 1], respectively. Since this instruction is an approximate operation instruction, an imprecision exception is always required (even if the input is a 0, the result is imprecise).","void FSCA (int n) {
 if (FPSCR_PR != 0)
 undefined_operation ();
 else
 {
 float angle;
 long offset = 0x00010000;
 long fraction = 0x0000FFFF;
 set_I ();
 fraction &= FPUL; // extract sub-rotation (fraction) part
 angle = fraction; // convert to float
 angle = 2 * M_PI * angle / offset; // convert to radian
 FR[n] = sin (angle);
 FR[n+1] = cos (angle);
 PC += 2;
 }
}"
fabs DRn,1111nnn001011101,DRn & 0x7FFFFFFFFFFFFFFF -> DRn,"Clears the most significant bit of the contents of floating-point register DRn to 0, and stores the result in DRn.","void FABS (int n) {
 FR[n] = FR[n] & 0x7FFFFFFFF;
 PC += 2;
}"
fneg DRn,1111nnn001001101,DRn ^ 0x8000000000000000 -> DRn,"Inverts the most significant bit (sign bit) of the contents of floating-point register DRn, and stores the result in DRn.","void FNEG (int n) {
 FR[n] = -FR[n];
 PC += 2;
}"
"dct plds Dz,MACH",111110********** 111011100000zzzz,If DC = 1: Dz -> MACH Else: nop,"Conditionally stores the Dz operand in the MACH register. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void plds_mach_dct (void) { if (DC == 1) MACH = DSP_REG[ex2_dz_no]; }
"dct plds Dz,MACL",111110********** 111111100000zzzz,If DC = 1: Dz -> MACL Else: nop,"Conditionally stores the Dz operand in the MACL register. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void plds_macl_dct (void) { if (DC == 1) MACL = DSP_REG[ex2_dz_no]; }
"dcf plds Dz,MACH",111110********** 111011110000zzzz,If DC = 0: Dz -> MACH Else: nop,"Conditionally stores the Dz operand in the MACH register. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void plds_mach_dcf (void) { if (DC == 0) MACH = DSP_REG[ex2_dz_no]; }
"dcf plds Dz,MACL",111110********** 111111110000zzzz,If DC = 0: Dz -> MACL Else: nop,"Conditionally stores the Dz operand in the MACL register. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void plds_macl_dcf (void) { if (DC == 0) MACL = DSP_REG[ex2_dz_no]; }
"psts MACH,Dz",111110********** 110011010000zzzz,MACH -> Dz,"Stores the contents of the MACH register in the Dz operand. The DC, N, Z, V, and GT bits of the DSR register are not updated.",void psts_mach (void) { DSP_REG[ex2_dz_no] = MACH; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } }
"sts FPUL,Rn",0000nnnn01011010,FPUL -> Rn,Stores FPU system register FPUL in the destination.,void STSFPUL (int n) { R[n] = FPUL; PC += 2; }
"lds.l @Rm+,FPUL",0100mmmm01010110,"(Rm) -> FPUL, Rm+4 -> Rm",,void LDSMFPUL (int m) { FPUL = Read_32 (R[m]); R[m] += 4; PC += 2; }
"sts.l FPUL,@-Rn",0100nnnn01010010,"Rn-4 -> Rn, FPUL -> (Rn)",Stores FPU system register FPUL in the destination.,"void STSMFPUL (int n) { R[n] -= 4; Write_32 (R[n], FPUL); PC += 2; }"
frchg,1111101111111101,If FPSCR.PR = 0: ~FPSCR.FR -> FPSCR.FR Else: Undefined Operation,"Inverts the FR bit in floating-point register FPSCR. When the FR bit in FPSCR is changed, FR0 to FR15 in FPR0_BANK0 to FPR15_BANK0 and FPR0_BANK1 to FPR15_BANK1 become XR0 to XR15, and XR0 to XR15 become FR0 to FR15. When FPSCR.FR = 0, FPR0_BANK0 to FPR15_BANK0 correspond to FR0 to FR15, and FPR0_BANK1 to FPR15_BANK1 correspond to XR0 to XR15. When FPSCR.FR = 1, FPR0_BANK1 to FPR15_BANK1 correspond to FR0 to FR15, and FPR0_BANK0 to FPR15_BANK0 correspond to XR0 to XR15.",void FRCHG (void) { if (FPSCR_PR == 0) { FPSCR ^= 0x00200000; // toggle bit 21 PC += 2; } else undefined_operation (); }
fschg,1111001111111101,If FPSCR.PR = 0: ~FPSCR.SZ -> FPSCR.SZ Else: Undefined Operation,"Inverts the SZ bit of the floating-point status register FPSCR. Changing the value of the SZ bit in FPSCR switches the amount of data for transfer by the FMOV instruction between one single-precision data and a pair of single-precision data. When FPSCR.SZ = 0, an FMOV instruction transfers a single-precision number. When FPSCR.SZ = 1, the FMOV instruction transfers a pair of single-precision numbers.",void FSCHG (void) { if (FPSCR_PR == 0) { FPSCR ^= 0x00100000; // toggle bit 20 PC += 2; } else undefined_operation (); }
fpchg,1111011111111101,~FPSCR.PR -> FPSCR.PR,Inverts the PR bit of the floating-point status register FPSCR. The value of this bit selects single-precision or double-precision operation.,void FPCHG (void) { FPSCR ^= 0x00080000; // toggle bit 19 PC += 2; }
nopx,1111000*0*0*00**,No operation,No access operation for X memory.,
"stc GBR,Rn",0000nnnn00010010,GBR -> Rn,Stores control register GBR in the destination.,STCGBR (int n) { R[n] = GBR; PC += 2; }
"stc.l GBR,@-Rn",0100nnnn00010011,"Rn-4 -> Rn, GBR -> (Rn)",Stores control register GBR in the destination.,"void STCMGBR (int n) { R[n] -= 4; Write_32 (R[n], GBR); PC += 2; }"
"stc VBR,Rn",0000nnnn00100010,VBR -> Rn,Stores control register VBR in the destination.,void STCVBR (int n) { R[n] = VBR; PC += 2; }
"stc.l VBR,@-Rn",0100nnnn00100011,"Rn-4 -> Rn, VBR -> (Rn)",Stores control register VBR in the destination.,"void STCMVBR (int n) { R[n] -= 4; Write_32 (R[n], VBR); PC += 2; }"
"stc MOD,Rn",0000nnnn01010010,MOD -> Rn,Stores control register MOD in the destination.,void STCMOD (int n) { R[n] = MOD; PC += 2; }
"stc.l MOD,@-Rn",0100nnnn01010011,"Rn-4 -> Rn, MOD -> (Rn)",Stores control register MOD in the destination.,"void STCMMOD (int n) { R[n] -= 4; Write_32 (R[n], MOD); PC += 2; }"
"stc RE,Rn",0000nnnn01110010,RE -> Rn,Stores control register RE in the destination.,void STCRE (int n) { R[n] = RE; PC += 2; }