statement stringlengths 1 2.09k | proof stringlengths 0 22.1k | type stringclasses 25
values | symbolic_name stringlengths 1 49 | library stringclasses 14
values | filename stringclasses 212
values | imports listlengths 0 63 | deps listlengths 0 64 | docstring stringlengths 0 1.82k | source_url stringclasses 1
value | commit stringclasses 1
value |
|---|---|---|---|---|---|---|---|---|---|---|
ptr64 | := true. | Definition | ptr64 | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
big_endian | := false. | Definition | big_endian | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
align_int64 | := 8%Z. | Definition | align_int64 | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
align_float64 | := 8%Z. | Definition | align_float64 | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
splitlong | := false. | Definition | splitlong | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
splitlong_ptr32: splitlong = true -> ptr64 = false. | Proof.
unfold splitlong, ptr64; congruence.
Qed. | Lemma | splitlong_ptr32 | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [
"ptr64",
"splitlong"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
default_nan_64 | := (false, iter_nat 51 _ xO xH). | Definition | default_nan_64 | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
default_nan_32 | := (false, iter_nat 22 _ xO xH). | Definition | default_nan_32 | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
choose_nan (is_signaling: positive -> bool)
(default: bool * positive)
(l0: list (bool * positive)) : bool * positive | :=
let fix choose_snan (l1: list (bool * positive)) :=
match l1 with
| nil =>
match l0 with nil => default | n :: _ => n end
| ((s, p) as n) :: l1 =>
if is_signaling p then n else choose_snan l1
end
in choose_snan l0. | Definition | choose_nan | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [
"default"
] | Choose the first signaling NaN, if any;
otherwise choose the first NaN;
otherwise use default. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
choose_nan_idem: forall is_signaling default n,
choose_nan is_signaling default (n :: n :: nil) =
choose_nan is_signaling default (n :: nil). | Proof.
intros. destruct n as [s p]; unfold choose_nan; simpl.
destruct (is_signaling p); auto.
Qed. | Lemma | choose_nan_idem | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [
"choose_nan",
"default"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
choose_nan_64 | :=
choose_nan (fun p => negb (Pos.testbit p 51)) default_nan_64. | Definition | choose_nan_64 | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [
"choose_nan",
"default_nan_64",
"testbit"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
choose_nan_32 | :=
choose_nan (fun p => negb (Pos.testbit p 22)) default_nan_32. | Definition | choose_nan_32 | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [
"choose_nan",
"default_nan_32",
"testbit"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
choose_nan_64_idem: forall n,
choose_nan_64 (n :: n :: nil) = choose_nan_64 (n :: nil). | Proof. intros; apply choose_nan_idem. Qed. | Lemma | choose_nan_64_idem | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [
"choose_nan_64",
"choose_nan_idem"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
choose_nan_32_idem: forall n,
choose_nan_32 (n :: n :: nil) = choose_nan_32 (n :: nil). | Proof. intros; apply choose_nan_idem. Qed. | Lemma | choose_nan_32_idem | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [
"choose_nan_32",
"choose_nan_idem"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
fma_order {A: Type} (x y z: A) | := (z, x, y). | Definition | fma_order | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
fma_invalid_mul_is_nan | := true. | Definition | fma_invalid_mul_is_nan | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
float_of_single_preserves_sNaN | := false. | Definition | float_of_single_preserves_sNaN | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
float_conversion_default_nan | := false. | Definition | float_conversion_default_nan | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
abi_kind: Type | :=
| AAPCS64 (**r ARM's standard as used in Linux and other ELF platforms *)
| Apple. | Inductive | abi_kind | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [] | Which ABI to implement | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
abi: abi_kind. | Parameter | abi | aarch64 | aarch64/Archi.v | [
"Coq",
"ZArith",
"List",
"Flocq",
"Binary",
"Bits"
] | [
"abi_kind"
] | r the variant used in macOS and iOS | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
ireg: Type | :=
| X0 | X1 | X2 | X3 | X4 | X5 | X6 | X7
| X8 | X9 | X10 | X11 | X12 | X13 | X14 | X15
| X16 | X17 | X18 | X19 | X20 | X21 | X22 | X23
| X24 | X25 | X26 | X27 | X28 | X29 | X30. | Inductive | ireg | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [] | In assembly files, [Xn] denotes the full 64-bit register
and [Wn] the low 32 bits of [Xn]. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
ireg0: Type | :=
| RR0 (r: ireg) | XZR. | Inductive | ireg0 | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"RR0",
"ireg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
iregsp: Type | :=
| RR1 (r: ireg) | XSP. | Inductive | iregsp | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"RR1",
"ireg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
RR0: ireg >-> ireg0. | Coercion | RR0 | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"ireg",
"ireg0"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | ||
RR1: ireg >-> iregsp. | Coercion | RR1 | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"ireg",
"iregsp"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | ||
ireg_eq: forall (x y: ireg), {x=y} + {x<>y}. | Proof. decide equality. Defined. | Lemma | ireg_eq | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"ireg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
freg: Type | :=
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7
| D8 | D9 | D10 | D11 | D12 | D13 | D14 | D15
| D16 | D17 | D18 | D19 | D20 | D21 | D22 | D23
| D24 | D25 | D26 | D27 | D28 | D29 | D30 | D31. | Inductive | freg | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [] | In assembly files, [Dn] denotes the low 64-bit of a vector register,
and [Sn] the low 32 bits. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
freg_eq: forall (x y: freg), {x=y} + {x<>y}. | Proof. decide equality. Defined. | Lemma | freg_eq | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"freg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
crbit: Type | :=
| CN: crbit (**r negative *)
| CZ: crbit (**r zero *)
| CC: crbit (**r carry *)
| CV: crbit. | Inductive | crbit | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [] | Bits in the condition register. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
crbit_eq: forall (x y: crbit), {x=y} + {x<>y}. | Proof. decide equality. Defined. | Lemma | crbit_eq | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"crbit"
] | r overflow | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
preg: Type | :=
| IR: ireg -> preg (**r 64- or 32-bit integer registers *)
| FR: freg -> preg (**r double- or single-precision float registers *)
| CR: crbit -> preg (**r bits in the condition register *)
| SP: preg (**r register X31 used as stack pointer *)
| PC: preg. | Inductive | preg | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"CR",
"FR",
"IR",
"SP",
"crbit",
"freg",
"ireg"
] | We model the following registers of the ARM architecture. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
IR: ireg >-> preg. | Coercion | IR | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"ireg",
"preg"
] | r program counter | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
FR: freg >-> preg. | Coercion | FR | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"freg",
"preg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | ||
CR: crbit >-> preg. | Coercion | CR | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"crbit",
"preg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | ||
preg_eq: forall (x y: preg), {x=y} + {x<>y}. | Proof. decide equality. apply ireg_eq. apply freg_eq. apply crbit_eq. Defined. | Lemma | preg_eq | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"crbit_eq",
"freg_eq",
"ireg_eq",
"preg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
t | := preg. | Definition | t | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"preg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
eq | := preg_eq. | Definition | eq | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"preg_eq"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
preg_of_iregsp (r: iregsp) : preg | :=
match r with RR1 r => IR r | XSP => SP end. | Definition | preg_of_iregsp | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"IR",
"RR1",
"SP",
"iregsp",
"preg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
preg_of_iregsp: iregsp >-> preg. | Coercion | preg_of_iregsp | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"iregsp",
"preg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | ||
"'RA'" | := X30 (only parsing) : asm. | Notation | 'RA' | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
label | := positive. | Definition | label | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [] | The instruction set. Most instructions correspond exactly to
actual AArch64 instructions. See the ARM reference manuals for more
details. Some instructions, described below, are
pseudo-instructions: they expand to canned instruction sequences
during the printing of the assembly code. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
isize: Type | :=
| W (**r 32-bit integer operation *)
| X. | Inductive | isize | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
fsize: Type | :=
| S (**r 32-bit, single-precision FP operation *)
| D. | Inductive | fsize | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [] | r 64-bit integer operation | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
testcond : Type | :=
| TCeq: testcond (**r equal *)
| TCne: testcond (**r not equal *)
| TChs: testcond (**r unsigned higher or same *)
| TClo: testcond (**r unsigned lower *)
| TCmi: testcond (**r negative *)
| TCpl: testcond (**r positive *)
| TChi: testcond (**r unsigned higher *)
| TCls: testcond... | Inductive | testcond | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [] | r 64-bit, double-precision FP operation | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
addressing: Type | :=
| ADimm (base: iregsp) (n: int64) (**r base plus immediate offset *)
| ADreg (base: iregsp) (r: ireg) (**r base plus reg *)
| ADlsl (base: iregsp) (r: ireg) (n: int) (**r base plus reg LSL n *)
| ADsxt (base: iregsp) (r: ireg) (n: int) (**r base plus SIGN-... | Inductive | addressing | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"ident",
"int",
"int64",
"ireg",
"iregsp",
"ptrofs"
] | r signed less than or equal | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
shift_op: Type | :=
| SOnone
| SOlsl (n: int)
| SOlsr (n: int)
| SOasr (n: int)
| SOror (n: int). | Inductive | shift_op | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"int"
] | r base plus offset; base is updated before | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
extend_op: Type | :=
| EOsxtb (n: int)
| EOsxth (n: int)
| EOsxtw (n: int)
| EOuxtb (n: int)
| EOuxth (n: int)
| EOuxtw (n: int)
| EOuxtx (n: int). | Inductive | extend_op | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"int"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
instruction: Type | :=
(** Branches *)
| Pb (lbl: label) (**r branch *)
| Pbc (c: testcond) (lbl: label) (**r conditional branch *)
| Pbl (id: ident) (sg: signature) (**r jump to function and link *)
| Pbs (id: ... | Inductive | instruction | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"addressing",
"builtin_arg",
"builtin_res",
"extend_op",
"external_function",
"float",
"float32",
"freg",
"fsize",
"ident",
"int",
"ireg",
"ireg0",
"iregsp",
"isize",
"label",
"preg",
"ptrofs",
"res",
"shift_op",
"signature",
"testcond"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
code | := list instruction. | Definition | code | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"instruction"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
function : Type | := mkfunction { fn_sig: signature; fn_code: code }. | Record | function | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"code",
"signature"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
fundef | := AST.fundef function. | Definition | fundef | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"function"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
program | := AST.program fundef unit. | Definition | program | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"fundef"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
regset | := Pregmap.t val. | Definition | regset | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"val"
] | The semantics operates over a single mapping from registers
(type [preg]) to values. We maintain (but do not enforce)
the convention that integer registers are mapped to values of
type [Tint], float registers to values of type [Tfloat],
and condition bits to either [Vzero] or [Vone]. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
genv | := Genv.t fundef unit. | Definition | genv | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"Genv",
"fundef"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
ir0w (rs: regset) (r: ireg0) : val | :=
match r with RR0 r => rs (IR r) | XZR => Vint Int.zero end. | Definition | ir0w | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"IR",
"RR0",
"ireg0",
"regset",
"val",
"zero"
] | The value of an [ireg0] is either the value of the integer register,
or 0. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
ir0x (rs: regset) (r: ireg0) : val | :=
match r with RR0 r => rs (IR r) | XZR => Vlong Int64.zero end. | Definition | ir0x | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"IR",
"RR0",
"ireg0",
"regset",
"val",
"zero"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
"a # b" | := (a b) (at level 1, only parsing) : asm. | Notation | a # b | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [] | Concise notations for accessing and updating the values of registers. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
"a # b <- c" | := (Pregmap.set b c a) (at level 1, b at next level) : asm. | Notation | a # b <- c | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"next",
"set"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
"a ## b" | := (ir0w a b) (at level 1, only parsing) : asm. | Notation | a ## b | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"ir0w"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
"a ### b" | := (ir0x a b) (at level 1, only parsing) : asm. | Notation | a ### b | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"ir0x"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
undef_regs (l: list preg) (rs: regset) : regset | :=
match l with
| nil => rs
| r :: l' => undef_regs l' (rs#r <- Vundef)
end. | Fixpoint | undef_regs | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"preg",
"regset"
] | Undefining some registers | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
undef_flags (rs: regset) : regset | :=
fun r => match r with CR _ => Vundef | _ => rs r end. | Definition | undef_flags | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"CR",
"regset"
] | Undefining the condition codes | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
set_pair (p: rpair preg) (v: val) (rs: regset) : regset | :=
match p with
| One r => rs#r <- v
| Twolong rhi rlo => rs#rhi <- (Val.hiword v) #rlo <- (Val.loword v)
end. | Definition | set_pair | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"hiword",
"loword",
"preg",
"regset",
"rpair",
"val"
] | Assigning a register pair | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
set_res (res: builtin_res preg) (v: val) (rs: regset) : regset | :=
match res with
| BR r => rs#r <- v
| BR_none => rs
| BR_splitlong hi lo => set_res lo (Val.loword v) (set_res hi (Val.hiword v) rs)
end. | Fixpoint | set_res | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"builtin_res",
"hiword",
"loword",
"preg",
"regset",
"res",
"val"
] | Assigning the result of a builtin | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
symbol_low: genv -> ident -> ptrofs -> val. | Parameter | symbol_low | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"genv",
"ident",
"ptrofs",
"val"
] | The two functions below axiomatize how the linker processes
symbolic references [symbol + offset]. It computes the
difference between the address and the PC, and splits it into:
- 12 low bits usable as an offset in an addressing mode;
- 21 high bits usable as argument to the ADRP instruction.
In CompCert's ... | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
symbol_high: genv -> ident -> ptrofs -> val. | Parameter | symbol_high | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"genv",
"ident",
"ptrofs",
"val"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | ||
symbol_high_low:
forall (ge: genv) (id: ident) (ofs: ptrofs),
Val.addl (symbol_high ge id ofs) (symbol_low ge id ofs) = Genv.symbol_address ge id ofs. | Axiom | symbol_high_low | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"Genv",
"addl",
"ge",
"genv",
"ident",
"ptrofs",
"symbol_address",
"symbol_high",
"symbol_low"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | ||
find_instr (pos: Z) (c: code) {struct c} : option instruction | :=
match c with
| nil => None
| i :: il => if zeq pos 0 then Some i else find_instr (pos - 1) il
end. | Fixpoint | find_instr | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"code",
"instruction",
"zeq"
] | Looking up instructions in a code sequence by position. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
is_label (lbl: label) (instr: instruction) : bool | :=
match instr with
| Plabel lbl' => if peq lbl lbl' then true else false
| _ => false
end. | Definition | is_label | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"instruction",
"label",
"peq"
] | Position corresponding to a label | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
is_label_correct:
forall lbl instr,
if is_label lbl instr then instr = Plabel lbl else instr <> Plabel lbl. | Proof.
intros. destruct instr; simpl; try discriminate. destruct (peq lbl lbl0); congruence.
Qed. | Lemma | is_label_correct | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"is_label",
"peq"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
label_pos (lbl: label) (pos: Z) (c: code) {struct c} : option Z | :=
match c with
| nil => None
| instr :: c' =>
if is_label lbl instr then Some (pos + 1) else label_pos lbl (pos + 1) c'
end. | Fixpoint | label_pos | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"code",
"is_label",
"label"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
outcome: Type | :=
| Next: regset -> mem -> outcome
| Stuck: outcome. | Inductive | outcome | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"mem",
"regset"
] | The semantics is purely small-step and defined as a function
from the current state (a register set + a memory state)
to either [Next rs' m'] where [rs'] and [m'] are the updated register
set and memory state after execution of the instruction at [rs#PC],
or [Stuck] if the processor is stuck. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
nextinstr (rs: regset) | :=
rs#PC <- (Val.offset_ptr rs#PC Ptrofs.one). | Definition | nextinstr | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"offset_ptr",
"one",
"regset"
] | Manipulations over the [PC] register: continuing with the next
instruction ([nextinstr]) or branching to a label ([goto_label]). | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
goto_label (f: function) (lbl: label) (rs: regset) (m: mem) | :=
match label_pos lbl 0 (fn_code f) with
| None => Stuck
| Some pos =>
match rs#PC with
| Vptr b ofs => Next (rs#PC <- (Vptr b (Ptrofs.repr pos))) m
| _ => Stuck
end
end. | Definition | goto_label | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"function",
"label",
"label_pos",
"mem",
"regset",
"repr"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
eval_testcond (c: testcond) (rs: regset) : option bool | :=
match c with
| TCeq => (**r equal *)
match rs#CZ with
| Vint n => Some (Int.eq n Int.one)
| _ => None
end
| TCne => (**r not equal *)
match rs#CZ with
| Vint n => Some (Int.eq n Int.zero)
| _ => None
end
|... | Definition | eval_testcond | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"eq",
"one",
"regset",
"testcond",
"xor",
"zero"
] | Testing a condition | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
eval_testzero (sz: isize) (v: val) (m: mem): option bool | :=
match sz with
| W => Val.cmpu_bool (Mem.valid_pointer m) Ceq v (Vint Int.zero)
| X => Val.cmplu_bool (Mem.valid_pointer m) Ceq v (Vlong Int64.zero)
end. | Definition | eval_testzero | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"cmplu_bool",
"cmpu_bool",
"isize",
"mem",
"val",
"valid_pointer",
"zero"
] | Integer "is zero?" test | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
eval_testbit (sz: isize) (v: val) (n: int): option bool | :=
match sz with
| W => Val.cmp_bool Cne (Val.and v (Vint (Int.shl Int.one n))) (Vint Int.zero)
| X => Val.cmpl_bool Cne (Val.andl v (Vlong (Int64.shl' Int64.one n))) (Vlong Int64.zero)
end. | Definition | eval_testbit | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"and",
"andl",
"cmp_bool",
"cmpl_bool",
"int",
"isize",
"one",
"shl",
"shl'",
"val",
"zero"
] | Integer "bit is set?" test | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
eval_addressing (a: addressing) (rs: regset): val | :=
match a with
| ADimm base n => Val.addl rs#base (Vlong n)
| ADreg base r => Val.addl rs#base rs#r
| ADlsl base r n => Val.addl rs#base (Val.shll rs#r (Vint n))
| ADsxt base r n => Val.addl rs#base (Val.shll (Val.longofint rs#r) (Vint n))
| ADuxt base r n => Val.addl rs#base (Val.shll (Val.longofintu rs#r... | Definition | eval_addressing | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"addl",
"addressing",
"ge",
"longofint",
"longofintu",
"regset",
"shll",
"symbol_low",
"val"
] | Evaluating an addressing mode | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
exec_load (chunk: memory_chunk) (transf: val -> val)
(a: addressing) (r: preg) (rs: regset) (m: mem) | :=
match Mem.loadv chunk m (eval_addressing a rs) with
| None => Stuck
| Some v => Next (nextinstr (rs#r <- (transf v))) m
end. | Definition | exec_load | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"addressing",
"eval_addressing",
"loadv",
"mem",
"memory_chunk",
"nextinstr",
"preg",
"regset",
"val"
] | Auxiliaries for memory accesses | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
exec_store (chunk: memory_chunk)
(a: addressing) (v: val)
(rs: regset) (m: mem) | :=
match Mem.storev chunk m (eval_addressing a rs) v with
| None => Stuck
| Some m' => Next (nextinstr rs) m'
end. | Definition | exec_store | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"addressing",
"eval_addressing",
"mem",
"memory_chunk",
"nextinstr",
"regset",
"storev",
"val"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
compare_int (rs: regset) (v1 v2: val) (m: mem) | :=
rs#CN <- (Val.negative (Val.sub v1 v2))
#CZ <- (Val.cmpu (Mem.valid_pointer m) Ceq v1 v2)
#CC <- (Val.cmpu (Mem.valid_pointer m) Cge v1 v2)
#CV <- (Val.sub_overflow v1 v2). | Definition | compare_int | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"cmpu",
"mem",
"negative",
"regset",
"sub",
"sub_overflow",
"val",
"valid_pointer"
] | Comparisons | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
compare_long (rs: regset) (v1 v2: val) (m: mem) | :=
rs#CN <- (Val.negativel (Val.subl v1 v2))
#CZ <- (Val.maketotal (Val.cmplu (Mem.valid_pointer m) Ceq v1 v2))
#CC <- (Val.maketotal (Val.cmplu (Mem.valid_pointer m) Cge v1 v2))
#CV <- (Val.subl_overflow v1 v2). | Definition | compare_long | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"cmplu",
"maketotal",
"mem",
"negativel",
"regset",
"subl",
"subl_overflow",
"val",
"valid_pointer"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
compare_float (rs: regset) (v1 v2: val) | :=
match v1, v2 with
| Vfloat f1, Vfloat f2 =>
rs#CN <- (Val.of_bool (Float.cmp Clt f1 f2))
#CZ <- (Val.of_bool (Float.cmp Ceq f1 f2))
#CC <- (Val.of_bool (negb (Float.cmp Clt f1 f2)))
#CV <- (Val.of_bool (negb (Float.ordered f1 f2)))
| _, _ =>
rs#CN <- Vundef
#CZ <- Vu... | Definition | compare_float | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"cmp",
"of_bool",
"ordered",
"regset",
"val"
] | Semantics of [fcmp] instructions:
<<
== N=0 Z=1 C=1 V=0
< N=1 Z=0 C=0 V=0
> N=0 Z=0 C=1 V=0
unord N=0 Z=0 C=1 V=1
>> | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
compare_single (rs: regset) (v1 v2: val) | :=
match v1, v2 with
| Vsingle f1, Vsingle f2 =>
rs#CN <- (Val.of_bool (Float32.cmp Clt f1 f2))
#CZ <- (Val.of_bool (Float32.cmp Ceq f1 f2))
#CC <- (Val.of_bool (negb (Float32.cmp Clt f1 f2)))
#CV <- (Val.of_bool (negb (Float32.ordered f1 f2)))
| _, _ =>
rs#CN <- Vundef
... | Definition | compare_single | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"cmp",
"of_bool",
"ordered",
"regset",
"val"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
insert_in_int (x: val) (y: Z) (pos: Z) (len: Z) : val | :=
match x with
| Vint n => Vint (Int.repr (Zinsert (Int.unsigned n) y pos len))
| _ => Vundef
end. | Definition | insert_in_int | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"Zinsert",
"repr",
"unsigned",
"val"
] | Insertion of bits into an integer | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
insert_in_long (x: val) (y: Z) (pos: Z) (len: Z) : val | :=
match x with
| Vlong n => Vlong (Int64.repr (Zinsert (Int64.unsigned n) y pos len))
| _ => Vundef
end. | Definition | insert_in_long | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"Zinsert",
"repr",
"unsigned",
"val"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
eval_shift_op_int (v: val) (s: shift_op): val | :=
match s with
| SOnone => v
| SOlsl n => Val.shl v (Vint n)
| SOlsr n => Val.shru v (Vint n)
| SOasr n => Val.shr v (Vint n)
| SOror n => Val.ror v (Vint n)
end. | Definition | eval_shift_op_int | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"ror",
"shift_op",
"shl",
"shr",
"shru",
"val"
] | Evaluation of shifted operands | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
eval_shift_op_long (v: val) (s: shift_op): val | :=
match s with
| SOnone => v
| SOlsl n => Val.shll v (Vint n)
| SOlsr n => Val.shrlu v (Vint n)
| SOasr n => Val.shrl v (Vint n)
| SOror n => Val.rorl v (Vint n)
end. | Definition | eval_shift_op_long | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"rorl",
"shift_op",
"shll",
"shrl",
"shrlu",
"val"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
eval_extend (v: val) (x: extend_op): val | :=
match x with
| EOsxtb n => Val.shll (Val.longofint (Val.sign_ext 8 v)) (Vint n)
| EOsxth n => Val.shll (Val.longofint (Val.sign_ext 16 v)) (Vint n)
| EOsxtw n => Val.shll (Val.longofint v) (Vint n)
| EOuxtb n => Val.shll (Val.longofintu (Val.zero_ext 8 v)) (Vint n)
| EOuxth n => Val.shll (Val.longofintu ... | Definition | eval_extend | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"extend_op",
"longofint",
"longofintu",
"shll",
"sign_ext",
"val",
"zero_ext"
] | Evaluation of sign- or zero- extended operands | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
float32_of_bits (v: val): val | :=
match v with
| Vint n => Vsingle (Float32.of_bits n)
| _ => Vundef
end. | Definition | float32_of_bits | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"of_bits",
"val"
] | Bit-level conversion from integers to FP numbers | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
float64_of_bits (v: val): val | :=
match v with
| Vlong n => Vfloat (Float.of_bits n)
| _ => Vundef
end. | Definition | float64_of_bits | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"of_bits",
"val"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
exec_instr (f: function) (i: instruction) (rs: regset) (m: mem) : outcome | :=
match i with
(** Branches *)
| Pb lbl =>
goto_label f lbl rs m
| Pbc cond lbl =>
match eval_testcond cond rs with
| Some true => goto_label f lbl rs m
| Some false => Next (nextinstr rs) m
| None => Stuck
end
| Pbl id sg =>
Next (rs#RA <- (Val.offset_ptr rs#PC Ptro... | Definition | exec_instr | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"Genv",
"SP",
"absf",
"absfs",
"add",
"addf",
"addfs",
"addl",
"alloc",
"and",
"andl",
"compare_float",
"compare_int",
"compare_long",
"compare_single",
"divf",
"divfs",
"divls",
"divlu",
"divs",
"divu",
"eval_extend",
"eval_shift_op_int",
"eval_shift_op_long",
"eval_... | Execution of a single instruction [i] in initial state
[rs] and [m]. Return updated state. For instructions
that correspond to actual AArch64 instructions, the cases are
straightforward transliterations of the informal descriptions
given in the ARMv8 reference manuals. For pseudo-instructions,
re... | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
preg_of (r: mreg) : preg | :=
match r with
| R0 => X0 | R1 => X1 | R2 => X2 | R3 => X3
| R4 => X4 | R5 => X5 | R6 => X6 | R7 => X7
| R8 => X8 | R9 => X9 | R10 => X10 | R11 => X11
| R12 => X12 | R13 => X13 | R14 => X14 | R15 => X15
| R17 => X17 | R19 => X19
| R20 => X20 | R21 => X21 | R22 => X22 | R23 => X23
| R24 ... | Definition | preg_of | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"mreg",
"preg"
] | Translation of the LTL/Linear/Mach view of machine registers
to the AArch64 view. Note that no LTL register maps to [X16],
[X18], nor [X30].
[X18] is reserved as the platform register and never used by the
code generated by CompCert.
[X30] is used for the return address, and can also be used as temporary.
... | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
undef_caller_save_regs (rs: regset) : regset | :=
fun r =>
if preg_eq r SP
|| In_dec preg_eq r (List.map preg_of (List.filter is_callee_save all_mregs))
then rs r
else Vundef. | Definition | undef_caller_save_regs | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"In_dec",
"SP",
"all_mregs",
"is_callee_save",
"map",
"preg_eq",
"preg_of",
"regset"
] | Undefine all registers except SP and callee-save registers | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
extcall_arg (rs: regset) (m: mem): loc -> val -> Prop | :=
| extcall_arg_reg: forall r,
extcall_arg rs m (R r) (rs (preg_of r))
| extcall_arg_stack: forall ofs ty bofs v,
bofs = Stacklayout.fe_ofs_arg + 4 * ofs ->
Mem.loadv (chunk_of_type ty) m
(Val.offset_ptr rs#SP (Ptrofs.repr bofs)) = Some v ->
extcall_arg rs m (Locations.S Out... | Inductive | extcall_arg | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"SP",
"chunk_of_type",
"fe_ofs_arg",
"loadv",
"loc",
"mem",
"offset_ptr",
"preg_of",
"regset",
"repr",
"val"
] | Extract the values of the arguments of an external call.
We exploit the calling conventions from module [Conventions], except that
we use AArch64 registers instead of locations. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
extcall_arg_pair (rs: regset) (m: mem): rpair loc -> val -> Prop | :=
| extcall_arg_one: forall l v,
extcall_arg rs m l v ->
extcall_arg_pair rs m (One l) v
| extcall_arg_twolong: forall hi lo vhi vlo,
extcall_arg rs m hi vhi ->
extcall_arg rs m lo vlo ->
extcall_arg_pair rs m (Twolong hi lo) (Val.longofwords vhi vlo). | Inductive | extcall_arg_pair | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"extcall_arg",
"loc",
"longofwords",
"mem",
"regset",
"rpair",
"val"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
extcall_arguments
(rs: regset) (m: mem) (sg: signature) (args: list val) : Prop | :=
list_forall2 (extcall_arg_pair rs m) (loc_arguments sg) args. | Definition | extcall_arguments | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"extcall_arg_pair",
"list_forall2",
"loc_arguments",
"mem",
"regset",
"signature",
"val"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loc_external_result (sg: signature) : rpair preg | :=
map_rpair preg_of (loc_result sg). | Definition | loc_external_result | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"loc_result",
"map_rpair",
"preg",
"preg_of",
"rpair",
"signature"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
state: Type | :=
| State: regset -> mem -> state. | Inductive | state | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"mem",
"regset"
] | Execution of the instruction at [rs#PC]. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
step: state -> trace -> state -> Prop | :=
| exec_step_internal:
forall b ofs f i rs m rs' m',
rs PC = Vptr b ofs ->
Genv.find_funct_ptr ge b = Some (Internal f) ->
find_instr (Ptrofs.unsigned ofs) f.(fn_code) = Some i ->
exec_instr f i rs m = Next rs' m' ->
step (State rs m) E0 (State rs' m')
| exec_step_builtin:
... | Inductive | step | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"E0",
"Genv",
"IR",
"SP",
"destroyed_by_builtin",
"ef_sig",
"eval_builtin_args",
"exec_instr",
"extcall_arguments",
"external_call",
"find_funct_ptr",
"find_instr",
"ge",
"loc_external_result",
"map",
"nextinstr",
"preg_of",
"res",
"set_pair",
"set_res",
"state",
"trace",
... | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
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