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| module cofiber_detector #( |
| parameter FEAT_DIM = 768, |
| parameter NUM_CLASSES = 80, |
| parameter BIT_WIDTH = 8, |
| parameter ACC_WIDTH = 24 |
| )( |
| input logic signed [BIT_WIDTH-1:0] features [0:FEAT_DIM-1], |
| output logic signed [ACC_WIDTH-1:0] cls_scores [0:NUM_CLASSES-1], |
| output logic signed [ACC_WIDTH-1:0] box_ltrb [0:3], |
| output logic signed [ACC_WIDTH-1:0] centerness |
| ); |
|
|
| |
| logic signed [BIT_WIDTH-1:0] cls_weight [0:NUM_CLASSES-1][0:FEAT_DIM-1]; |
| logic signed [BIT_WIDTH-1:0] cls_bias [0:NUM_CLASSES-1]; |
| logic signed [BIT_WIDTH-1:0] reg_weight [0:3][0:FEAT_DIM-1]; |
| logic signed [BIT_WIDTH-1:0] reg_bias [0:3]; |
| logic signed [BIT_WIDTH-1:0] ctr_weight [0:FEAT_DIM-1]; |
| logic signed [BIT_WIDTH-1:0] ctr_bias; |
|
|
| initial begin |
| $readmemh("rom/cls_weight.hex", cls_weight); |
| $readmemh("rom/cls_bias.hex", cls_bias); |
| $readmemh("rom/reg_out_weight.hex", reg_weight); |
| $readmemh("rom/reg_out_bias.hex", reg_bias); |
| $readmemh("rom/ctr_weight.hex", ctr_weight); |
| $readmemh("rom/ctr_bias.hex", ctr_bias); |
| end |
|
|
| |
| |
| genvar c, d; |
| generate |
| for (c = 0; c < NUM_CLASSES; c = c + 1) begin : cls_mac |
| logic signed [ACC_WIDTH-1:0] acc; |
| always_comb begin |
| acc = {{(ACC_WIDTH-BIT_WIDTH){cls_bias[c][BIT_WIDTH-1]}}, cls_bias[c]}; |
| for (int dd = 0; dd < FEAT_DIM; dd = dd + 1) begin |
| acc = acc + (features[dd] * cls_weight[c][dd]); |
| end |
| cls_scores[c] = acc; |
| end |
| end |
| endgenerate |
|
|
| |
| generate |
| for (c = 0; c < 4; c = c + 1) begin : reg_mac |
| logic signed [ACC_WIDTH-1:0] acc; |
| always_comb begin |
| acc = {{(ACC_WIDTH-BIT_WIDTH){reg_bias[c][BIT_WIDTH-1]}}, reg_bias[c]}; |
| for (int dd = 0; dd < FEAT_DIM; dd = dd + 1) begin |
| acc = acc + (features[dd] * reg_weight[c][dd]); |
| end |
| box_ltrb[c] = acc; |
| end |
| end |
| endgenerate |
|
|
| |
| logic signed [ACC_WIDTH-1:0] ctr_acc; |
| always_comb begin |
| ctr_acc = {{(ACC_WIDTH-BIT_WIDTH){ctr_bias[BIT_WIDTH-1]}}, ctr_bias}; |
| for (int dd = 0; dd < FEAT_DIM; dd = dd + 1) begin |
| ctr_acc = ctr_acc + (features[dd] * ctr_weight[dd]); |
| end |
| centerness = ctr_acc; |
| end |
|
|
| endmodule |
|
|
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| |
| |
| module cofiber_decompose #( |
| parameter FEAT_DIM = 768, |
| parameter BIT_WIDTH = 8, |
| parameter H = 40, |
| parameter W = 40 |
| )( |
| input logic signed [BIT_WIDTH-1:0] features [0:FEAT_DIM-1][0:H-1][0:W-1], |
| output logic signed [BIT_WIDTH-1:0] scale0 [0:FEAT_DIM-1][0:H-1][0:W-1], |
| output logic signed [BIT_WIDTH-1:0] scale1 [0:FEAT_DIM-1][0:H/2-1][0:W/2-1], |
| output logic signed [BIT_WIDTH-1:0] scale2 [0:FEAT_DIM-1][0:H/4-1][0:W/4-1] |
| ); |
|
|
| |
| logic signed [BIT_WIDTH+1:0] pool0 [0:FEAT_DIM-1][0:H/2-1][0:W/2-1]; |
| logic signed [BIT_WIDTH+1:0] pool1 [0:FEAT_DIM-1][0:H/4-1][0:W/4-1]; |
|
|
| genvar ch, r, col; |
| generate |
| |
| for (ch = 0; ch < FEAT_DIM; ch = ch + 1) begin : pool0_ch |
| for (r = 0; r < H/2; r = r + 1) begin : pool0_r |
| for (col = 0; col < W/2; col = col + 1) begin : pool0_c |
| assign pool0[ch][r][col] = (features[ch][2*r][2*col] |
| + features[ch][2*r+1][2*col] |
| + features[ch][2*r][2*col+1] |
| + features[ch][2*r+1][2*col+1]) >>> 2; |
| end |
| end |
| end |
|
|
| |
| |
| for (ch = 0; ch < FEAT_DIM; ch = ch + 1) begin : s0_ch |
| for (r = 0; r < H; r = r + 1) begin : s0_r |
| for (col = 0; col < W; col = col + 1) begin : s0_c |
| assign scale0[ch][r][col] = features[ch][r][col] |
| - pool0[ch][r/2][col/2][BIT_WIDTH-1:0]; |
| end |
| end |
| end |
|
|
| |
| for (ch = 0; ch < FEAT_DIM; ch = ch + 1) begin : pool1_ch |
| for (r = 0; r < H/4; r = r + 1) begin : pool1_r |
| for (col = 0; col < W/4; col = col + 1) begin : pool1_c |
| assign pool1[ch][r][col] = (pool0[ch][2*r][2*col] |
| + pool0[ch][2*r+1][2*col] |
| + pool0[ch][2*r][2*col+1] |
| + pool0[ch][2*r+1][2*col+1]) >>> 2; |
| end |
| end |
| end |
|
|
| |
| for (ch = 0; ch < FEAT_DIM; ch = ch + 1) begin : s1_ch |
| for (r = 0; r < H/2; r = r + 1) begin : s1_r |
| for (col = 0; col < W/2; col = col + 1) begin : s1_c |
| assign scale1[ch][r][col] = pool0[ch][r][col][BIT_WIDTH-1:0] |
| - pool1[ch][r/2][col/2][BIT_WIDTH-1:0]; |
| end |
| end |
| end |
|
|
| |
| for (ch = 0; ch < FEAT_DIM; ch = ch + 1) begin : s2_ch |
| for (r = 0; r < H/4; r = r + 1) begin : s2_r |
| for (col = 0; col < W/4; col = col + 1) begin : s2_c |
| assign scale2[ch][r][col] = pool1[ch][r][col][BIT_WIDTH-1:0]; |
| end |
| end |
| end |
| endgenerate |
|
|
| endmodule |
|
|