DiT engines: replace BF16 with FP16-mixed (FP32 islands) + add FP32 variants

DiT TRT engines: rebuild with profile min=1 (sm_90)

T5Gemma: FP16-mixed (FP32 attention island) — fixes BF16 numerical bug

Decoder TRT engines: PCM-baked-in (sm_90)

Drop L-range suffix from SAME-L decoder filename

Reorganize tensorRT/ into per-arch subdirs; rebuild DiT engines with conditioner baked in

Remove padding_embedding.pt — these ship with the inference code repo

Remove pipeline_state from tensorRT/ — it ships with the inference code repo, not here

Add pipeline_state + per-model padding_embedding for SA3 TRT pipeline

Add SA3 TRT engines (LFS-tracked)

Create tensorRT/README.md