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@@ -11,6 +11,17 @@ pipeline_tag: text-generation
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  [Project page](https://iprc-dip.github.io/CodeV-R1)
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  ### 1. Introduction
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  Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification, such as software programming and mathematical problems. Extending RLVR to electronic design automation (EDA), especially automatically generating hardware description languages (HDLs) like Verilog from natural-language (NL) specifications, however, poses three key challenges: the lack of automated and accurate verification environments, the scarcity of high‐quality NL–code pairs, and the prohibitive computation cost of RLVR.
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  | **CodeV-R1-distill (ours)** | 7B | Verilog RTL | 56.2% |
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  | **CodeV-R1 (ours)** | 7B | Verilog RTL | **72.9%** |
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- We also plot the results for RTLLM v1.1, including pass rate against model size and test-time scaling under different token/FLOPs budgets.
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  <div style="display: flex; gap: 10px;">
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  <img src="./assets/rtllm_acc_vs_model_size.png" alt="RTLLM TTS Results" width="1200">
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  </div>
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- <div style="display: flex; gap: 10px;">
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- <img src="./assets/rtllm_tts.png" alt="RTLLM TTS Results" width="500">
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- <img src="./assets/rtllm_tts_flops.png" alt="RTLLM TTS FLOPs Results" width="500">
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- </div>
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  ### 4. Usage
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  [Project page](https://iprc-dip.github.io/CodeV-R1)
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+ <div class="figure-container" style="display: flex; flex-direction: column; gap: 15px; max-width: 850px;">
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+ <div style="display: flex; gap: 10px; justify-content: center;">
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+ <img src="./assets/rtllm_tts.png" alt="RTLLM TTS Results" width="400">
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+ <img src="./assets/rtllm_tts_flops.png" alt="RTLLM TTS FLOPs Results" width="400">
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+ </div>
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+ <figcaption class="caption mt-3 has-text-centered is-size-7 has-text-grey">
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+ Test-time scaling curves. Left: Inference time as a function of token length. Right: Inference time vs. estimated FLOPs consumption.
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+ When measured by FLOPs consumption, our model achieves better results with fewer computational resources than DeepSeek-R1, highlighting its superior efficiency.
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+ </figcaption>
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+ </div>
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+
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  ### 1. Introduction
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  Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification, such as software programming and mathematical problems. Extending RLVR to electronic design automation (EDA), especially automatically generating hardware description languages (HDLs) like Verilog from natural-language (NL) specifications, however, poses three key challenges: the lack of automated and accurate verification environments, the scarcity of high‐quality NL–code pairs, and the prohibitive computation cost of RLVR.
 
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  | **CodeV-R1-distill (ours)** | 7B | Verilog RTL | 56.2% |
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  | **CodeV-R1 (ours)** | 7B | Verilog RTL | **72.9%** |
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+ For RTLLM v1.1, we also plot results showing pass rate against model size.
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  <div style="display: flex; gap: 10px;">
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  <img src="./assets/rtllm_acc_vs_model_size.png" alt="RTLLM TTS Results" width="1200">
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  </div>
 
 
 
 
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  ### 4. Usage
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