task_id stringlengths 16 24 | shuttle_name stringclasses 7
values | project_name stringlengths 12 79 | task_name stringlengths 7 59 | top_module_name stringlengths 9 54 | system_message stringclasses 1
value | prompt stringlengths 724 368k | golden_module stringlengths 66 320k |
|---|---|---|---|---|---|---|---|
ttsky25a-finale_1101 | ttsky25a-finale | tapeoutcutm-High-Speed-8-8-Vedic-Multiplier-for-Efficient-Arithmetic-Operations | task_tt_um_vedic_4x4 | tt_um_vedic_4x4 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_vedic_4x4 (
input [7:0] ui_in, // ui_in[3:0] = a, ui_in[7:4] = b
output [7:0] uo_out, // r = a × b
input [7:0] uio_in, // unused
output [7:0] uio_out, // unused
output [7:0] uio_oe, // unused
input clk, // unused
input rst_n, // unused
input... | module tt_um_vedic_4x4 (
input [7:0] ui_in, // ui_in[3:0] = a, ui_in[7:4] = b
output [7:0] uo_out, // r = a × b
input [7:0] uio_in, // unused
output [7:0] uio_out, // unused
output [7:0] uio_oe, // unused
input clk, // unused
input rst_n, // unused
input... |
ttsky25a-finale_1102 | ttsky25a-finale | tapeoutcutm-High-Speed-8-8-Vedic-Multiplier-for-Efficient-Arithmetic-Operations | task_vedic2 | tt_um_vedic_4x4 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_vedic_4x4 (
input [7:0] ui_in, // ui_in[3:0] = a, ui_in[7:4] = b
output [7:0] uo_out, // r = a × b
input [7:0] uio_in, // unused
output [7:0] uio_out, // unused
output [7:0] uio_oe, // unused
input clk, // unused
input rst_n, // unused
input... | module vedic2 (
input [1:0] a,
input [1:0] b,
output [3:0] r
);
wire p0, p1, p2, p3;
wire s1, c1, s2, c2;
assign p0 = a[0] & b[0];
assign p1 = a[1] & b[0];
assign p2 = a[0] & b[1];
assign p3 = a[1] & b[1];
assign s1 = p1 ^ p2;
assign c1 = p1 & p2;
assign s2 = p3 ^ c1;
... |
ttsky25a-finale_1103 | ttsky25a-finale | tapeoutcutm-High-Speed-8-8-Vedic-Multiplier-for-Efficient-Arithmetic-Operations | task_vedic4 | tt_um_vedic_4x4 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_vedic_4x4 (
input [7:0] ui_in, // ui_in[3:0] = a, ui_in[7:4] = b
output [7:0] uo_out, // r = a × b
input [7:0] uio_in, // unused
output [7:0] uio_out, // unused
output [7:0] uio_oe, // unused
input clk, // unused
input rst_n, // unused
input... | module vedic4 (
input [3:0] a,
input [3:0] b,
output [7:0] r
);
wire [3:0] p0, p1, p2, p3;
wire [7:0] temp1, temp2, temp3;
vedic2 v0 (a[1:0], b[1:0], p0);
vedic2 v1 (a[3:2], b[1:0], p1);
vedic2 v2 (a[1:0], b[3:2], p2);
vedic2 v3 (a[3:2], b[3:2], p3);
assign temp1 = {4'b0000, p1... |
ttsky25a-finale_1104 | ttsky25a-finale | tapeoutcutm-UART-protocol | task_tt_um_uart | tt_um_uart | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none //
module tt_um_uart (
input wire [7:0] ui_in, // control inputs
output wire [7:0] uo_out, // received data
input wire [7:0] uio_in, // tx_data (bits 7:1), rx_data (bit 0)
output wire [7:0] uio_out, // tx line + interrupt flags
output wire [7:0] uio_oe, // out... | module tt_um_uart (
input wire [7:0] ui_in, // control inputs
output wire [7:0] uo_out, // received data
input wire [7:0] uio_in, // tx_data (bits 7:1), rx_data (bit 0)
output wire [7:0] uio_out, // tx line + interrupt flags
output wire [7:0] uio_oe, // output enable
input wire... |
ttsky25a-finale_1105 | ttsky25a-finale | tapeoutcutm-array_multiplier | task_array_mult8x8 | tt_um_mac_spst_tiny | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* MAC with SPST adder (TinyTapeout compliant)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// ============================================================
// Top-level TinyTapeout wrapper
// ============================================================
module tt_um_mac_spst_tiny (
input wi... | module array_mult8x8 (
input wire [7:0] a,
input wire [7:0] b,
output wire [15:0] y
);
assign y = a * b;
endmodule |
ttsky25a-finale_1106 | ttsky25a-finale | tapeoutcutm-array_multiplier | task_mac_spst_tiny | tt_um_mac_spst_tiny | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* MAC with SPST adder (TinyTapeout compliant)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// ============================================================
// Top-level TinyTapeout wrapper
// ============================================================
module tt_um_mac_spst_tiny (
input wi... | module mac_spst_tiny (
input wire clk,
input wire rst_n,
input wire acc_en,
input wire [7:0] in_a,
input wire [7:0] in_b,
output wire [7:0] out_low,
output wire [7:0] out_high,
output wire out_high_oe
);
reg [15:0] acc;
wire [15:0] mult_out;
... |
ttsky25a-finale_1107 | ttsky25a-finale | tapeoutcutm-array_multiplier | task_spst_adder16 | tt_um_mac_spst_tiny | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* MAC with SPST adder (TinyTapeout compliant)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// ============================================================
// Top-level TinyTapeout wrapper
// ============================================================
module tt_um_mac_spst_tiny (
input wi... | module spst_adder16 (
input wire [15:0] a,
input wire [15:0] b,
output wire [15:0] sum
);
assign sum = a + b; // Replace with SPST optimized logic if needed
endmodule |
ttsky25a-finale_1108 | ttsky25a-finale | tapeoutcutm-array_multiplier | task_tt_um_mac_spst_tiny | tt_um_mac_spst_tiny | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* MAC with SPST adder (TinyTapeout compliant)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// ============================================================
// Top-level TinyTapeout wrapper
// ============================================================
module tt_um_mac_spst_tiny (
input wi... | module tt_um_mac_spst_tiny (
input wire [7:0] ui_in, // Dedicated inputs: operand A
output wire [7:0] uo_out, // Dedicated outputs: accumulator low byte
input wire [7:0] uio_in, // IOs: input path (operand B / ext high byte in)
output wire [7:0] uio_out, // IOs: output path (accumulator high b... |
ttsky25a-finale_1109 | ttsky25a-finale | tc503-ttsky25a-countdown-timer | task_clock_divider | tt_um_tc503_countdown_timer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio... | module clock_divider (
input clk,
input reset,
output reg min_tick
);
// Adjust max_count for a 1-minute period based on your system clock frequency
// localparam MAX_COUNT = 960000000; // (clock_frequency * 60) - 1
// localparam BITS = 30;
// reg [BITS-1:0] counter; // BITS depends on MAX_C... |
ttsky25a-finale_1110 | ttsky25a-finale | tc503-ttsky25a-countdown-timer | task_countdown_timer | tt_um_tc503_countdown_timer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio... | module countdown_timer (
input clk,
input reset,
input countdown0,
input enc0_a,
input enc0_b,
input enc1_a,
input enc1_b,
input enc2_a,
input enc2_b,
output pwm0_out,
output pwm1_out,
output pwm2_out,
output reg [6:0] dis0_out,
output dis0_ctrl
);
wire enc0_a... |
ttsky25a-finale_1111 | ttsky25a-finale | tc503-ttsky25a-countdown-timer | task_seven_segment | tt_um_tc503_countdown_timer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio... | module seven_segment (
input wire clk,
input wire reset,
input wire load,
input wire [3:0] ten_count,
input wire [3:0] unit_count,
output reg [6:0] segments,
output reg digit
);
reg [3:0] ten_count_reg;
reg [3:0] unit_count_reg;
wire [3:0] ... |
ttsky25a-finale_1112 | ttsky25a-finale | tc503-ttsky25a-countdown-timer | task_tt_um_tc503_countdown_timer | tt_um_tc503_countdown_timer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio... | module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... |
ttsky25a-finale_1113 | ttsky25a-finale | tgrillz-tt_um_sixSidedDie | task_sevenSeg | tt_um_tgrillz_sixSidedDie | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2025 tgrillz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tgrillz_sixSidedDie #(parameter STATE = 8'b1000_0001)(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input p... | module sevenSeg (
input wire clk,
input wire rst_n,
input wire [7:0] inputNum,
output wire [6:0] out
);
reg [7:0] displayIt;
reg [6:0] outNum;
always @(posedge clk) begin
if (!rst_n) begin
displayIt <= 0;
end else begin
displayIt <= inputNum;
... |
ttsky25a-finale_1114 | ttsky25a-finale | vagesh007-CF-2024-TT12-11 | task_clk_div | tt_um_fifo | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_fifo #(parameter DSIZE=8, parameter ASIZE=4)
(
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire rst_n
);
assign uo_out = rdata;
wire ... | module clk_div(
input wire clk, // 100 MHz input clock
input wire r_rst, // active-high reset for rclk
input wire w_rst, // active-high reset for wclk
output reg wclk, // 50 MHz (÷2)
output reg rclk // ~33.3 MHz (÷3)
);
// Divide-by-2 for 50 MHz
always @(posedg... |
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