task_id stringlengths 16 24 | shuttle_name stringclasses 7
values | project_name stringlengths 12 79 | task_name stringlengths 7 59 | top_module_name stringlengths 9 54 | system_message stringclasses 1
value | prompt stringlengths 724 368k | golden_module stringlengths 66 320k |
|---|---|---|---|---|---|---|---|
tt06-finale_0101 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_minibyte_cu | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module minibyte_cu(
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//IR Input
input wire [7:0] ir_op_buss_in,
//ALU Flags Input
input wire [1:0] ccr_flag_zn_in,
//Control signal outputs
output reg set_a_out,
output reg set_m... |
tt06-finale_0102 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_minibyte_genmux_2x | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module minibyte_genmux_2x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
//Mux Select
input wire sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 0
i... |
tt06-finale_0103 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_minibyte_genmux_4x | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module minibyte_genmux_4x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
//Mux Select
input wire [1:0] sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
... |
tt06-finale_0104 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_minibyte_genmux_8x | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module minibyte_genmux_8x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
input wire [7:0] e_in,
input wire [7:0] f_in,
input wire [7:0] g_in,
input wire [7:0] h_in,
//Mux Select
input wire [2:0] sel_in,
... |
tt06-finale_0105 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_minibyte_genreg | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module minibyte_genreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or neged... |
tt06-finale_0106 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_minibyte_pcreg | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module minibyte_pcreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
input wire inc_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
alw... |
tt06-finale_0107 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_reg_ram_8B | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module reg_ram_8B(
//Input CLK and RST
input wire clk_in,
input wire rst_in,
//Input Addr
input wire [2:0] address,
//Input Data
input wire [7:0] data_in,
//Input WE and EN
input wire we_in,
input wire en_in,
//Output Data
output reg [7:0] data_out
);
//Data busse... |
tt06-finale_0108 | tt06-finale | zacharysfrazee-tt06-minibyte-cpu | task_tt_um_minibyte | tt_um_minibyte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, ... | module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt07-finale_0109 | tt07-finale | BTFLV-tt07-subleq-fram-cpu | task_SPI_FRAM_Interface | tt_um_btflv_subleq | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_btflv_subleq (
input wire [7:0] ui_in , // Dedicated inputs
output wire [7:0] uo_out , // Dedicated outputs
input wire [7:0] uio_in , // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe , // IOs: Enable path (active high: 0=input, 1=outp... | module SPI_FRAM_Interface (
input wire clk ,
input wire rst_n ,
input spi_miso,
output reg spi_mosi,
output reg spi_sck ,
output reg spi_cs ,
input wire [15:0] addr ,
input wire [15:0] data_i... |
tt07-finale_0110 | tt07-finale | BTFLV-tt07-subleq-fram-cpu | task_UART_Credits | tt_um_btflv_subleq | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_btflv_subleq (
input wire [7:0] ui_in , // Dedicated inputs
output wire [7:0] uo_out , // Dedicated outputs
input wire [7:0] uio_in , // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe , // IOs: Enable path (active high: 0=input, 1=outp... | module UART_Credits (
input wire clk ,
input wire rst_n,
output reg tx
);
reg [ 1:0] state = INIT ;
reg [31:0] clk_counter = 0 ;
reg [ 3:0] bit_counter = 0 ;
reg [ 3:0] char_counter = 0 ;
reg [ 7:0] tx_shi... |
tt07-finale_0111 | tt07-finale | BTFLV-tt07-subleq-fram-cpu | task_UART_Transmitter | tt_um_btflv_subleq | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_btflv_subleq (
input wire [7:0] ui_in , // Dedicated inputs
output wire [7:0] uo_out , // Dedicated outputs
input wire [7:0] uio_in , // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe , // IOs: Enable path (active high: 0=input, 1=outp... | module UART_Transmitter (
input wire clk ,
input wire rst_n ,
input wire tx_start,
input wire [7:0] tx_data ,
output reg tx ,
output reg tx_busy
);
reg [15:0] baud_counter;
reg [ 3:0] bit_counter ;
reg [ 7:0] shi... |
tt07-finale_0112 | tt07-finale | BTFLV-tt07-subleq-fram-cpu | task_tt_um_btflv_subleq | tt_um_btflv_subleq | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_btflv_subleq (
input wire [7:0] ui_in , // Dedicated inputs
output wire [7:0] uo_out , // Dedicated outputs
input wire [7:0] uio_in , // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe , // IOs: Enable path (active high: 0=input, 1=outp... | module tt_um_btflv_subleq (
input wire [7:0] ui_in , // Dedicated inputs
output wire [7:0] uo_out , // Dedicated outputs
input wire [7:0] uio_in , // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe , // IOs: Enable path (active high: 0=input, 1=output)
input wire ... |
tt07-finale_0113 | tt07-finale | JamesTimothyMeech-TT07-LFSR | task_flip_flop | tt_um_lfsr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_lfsr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module flip_flop(out, clock, reset, in);
input clock;
input reset;
input in;
output reg out;
always @(posedge clock or posedge reset)
begin
if (reset)
out = 0;
else
out = in;
end
endmodule |
tt07-finale_0114 | tt07-finale | JamesTimothyMeech-TT07-LFSR | task_linear_feedback_shift_register | tt_um_lfsr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_lfsr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module linear_feedback_shift_register(out, clock, reset, seed, load_seed);
output reg out;
input [31:0] seed;
input load_seed;
input reset;
input clock;
wire [31:0] flip_flop_outputs;
wire [31:0] flip_flop_inputs;
wire feedback1, feedback2, feedback3;
flip_flop flip_flop_instance[31:0] (flip_flop_outputs, cloc... |
tt07-finale_0115 | tt07-finale | JamesTimothyMeech-TT07-LFSR | task_one_bit_mux | tt_um_lfsr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_lfsr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module one_bit_mux(out, control, input_a, input_b);
output reg out;
input control, input_a, input_b;
wire not_control;
always @(control or not_control or input_a or input_b)
out = (control & input_a) | (not_control & input_b);
not (not_control, control);
endmodule |
tt07-finale_0116 | tt07-finale | JamesTimothyMeech-TT07-LFSR | task_tt_um_lfsr | tt_um_lfsr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_lfsr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module tt_um_lfsr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
inp... |
tt07-finale_0117 | tt07-finale | JamesTimothyMeech-TT07-LFSR | task_wb_lfsr | tt_um_lfsr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_lfsr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module wb_lfsr(i_clk, i_reset, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, o_wb_stall, o_wb_data, o_wb_ack);
input i_clk;
input i_reset;
input i_wb_cyc;
input i_wb_stb;
input i_wb_we;
input [2:0] i_wb_addr;
input[7:0] i_wb_data;
output reg o_wb_stall;
output reg o_wb_ack;
output reg o_wb_data;
reg [... |
tt07-finale_0118 | tt07-finale | Kevomlml-tt07_chipusm_neural_network | task_machine | tt_um_neural_network | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module machine (
input wire clk,
input wire reset,
input wire changes,
input wire finished,
output reg [1:0] state
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module perceptron(
input [7:0] in0,
input [7:0] in1,
input [7:0] in2,
input [7:0] i... | module machine (
input wire clk,
input wire reset,
input wire changes,
input wire finished,
output reg [1:0] state
);
parameter state_data_IN = 2'b00;
parameter state_data_BUFF = 2'b01;
parameter state_data_OUT = 2'b10;
//Definir current_state y next_state
reg [1:0] current_state, next_state;
al... |
tt07-finale_0119 | tt07-finale | Kevomlml-tt07_chipusm_neural_network | task_perceptron | tt_um_neural_network | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module machine (
input wire clk,
input wire reset,
input wire changes,
input wire finished,
output reg [1:0] state
);
parameter state_data_IN = 2'b00;
parameter state_data_BUFF = 2'b01;
parameter state_data_OUT = 2'b10;
//Definir current_state y next_state
reg [1:0] current_state, next_state;
al... | module perceptron(
input [7:0] in0,
input [7:0] in1,
input [7:0] in2,
input [7:0] in3,
input [7:0] weight0, //aaa
input [7:0] weight1,
input [7:0] weight2,
input [7:0] weight3,
input [7:0] bias,
input [7:0] threshold,
output reg [7:0] out
);
reg [7:0] sum_p;
reg [7:0] res;... |
tt07-finale_0120 | tt07-finale | Kevomlml-tt07_chipusm_neural_network | task_register_parameters | tt_um_neural_network | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module machine (
input wire clk,
input wire reset,
input wire changes,
input wire finished,
output reg [1:0] state
);
parameter state_data_IN = 2'b00;
parameter state_data_BUFF = 2'b01;
parameter state_data_OUT = 2'b10;
//Definir current_state y next_state
reg [1:0] current_state, next_state;
al... | module register_parameters(
input wire clk,
input wire reset,
input wire [7:0] data_in,
input [1:0] selector,
//output reg [7:0] th3,
output reg [7:0] b3,
output reg [7:0] w33,
output reg [7:0] w32,
output reg [7:0] w31,
output reg [7:0] w30,
//output reg [7:0] th2,
outp... |
tt07-finale_0121 | tt07-finale | Kevomlml-tt07_chipusm_neural_network | task_shift_register_inputs | tt_um_neural_network | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module machine (
input wire clk,
input wire reset,
input wire changes,
input wire finished,
output reg [1:0] state
);
parameter state_data_IN = 2'b00;
parameter state_data_BUFF = 2'b01;
parameter state_data_OUT = 2'b10;
//Definir current_state y next_state
reg [1:0] current_state, next_state;
al... | module shift_register_inputs(
input clk,rstn,
input [7:0] data_in,
input [1:0] selector, // From the state machine. Determines where do the neuron inputs come From
//input [1:0] selector_output,
// The outputs of the neurons0..3 are inputs to the shift register, so it can use them as inputs to... |
tt07-finale_0122 | tt07-finale | Kevomlml-tt07_chipusm_neural_network | task_tt_um_neural_network | tt_um_neural_network | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module machine (
input wire clk,
input wire reset,
input wire changes,
input wire finished,
output reg [1:0] state
);
parameter state_data_IN = 2'b00;
parameter state_data_BUFF = 2'b01;
parameter state_data_OUT = 2'b10;
//Definir current_state y next_state
reg [1:0] current_state, next_state;
al... | module tt_um_neural_network (
input wire clk,
input wire rst_n,
input wire [7:0] uio_in,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
output wire [7:0] uio_oe,
output wire [7:0] uio_out,
input wire ena
);
assign uio_oe = 0;
assign uio_out = 0;
// Señales internas
wire [1:0... |
tt07-finale_0123 | tt07-finale | KosugiSubaru-tt07-td4cpu | task_ALU_adder_4bit | tt_um_TD4_Assy_KosugiSubaru | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_TD4_Assy_KosugiSubaru (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... | module ALU_adder_4bit(in_a, in_b, out, ci, co);
input [3:0] in_a, in_b;
input ci;
output [3:0] out;
output co;
reg [3:0] out;
reg co;
always @(in_a or in_b or ci) begin
{co, out} <= in_a + in_b + ci;
end
endmodule |
tt07-finale_0124 | tt07-finale | KosugiSubaru-tt07-td4cpu | task_decoder | tt_um_TD4_Assy_KosugiSubaru | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_TD4_Assy_KosugiSubaru (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... | module decoder(op, c_n, s, ld_n);
input [3:0] op;
input c_n;
output [1:0] s;
output [3:0] ld_n;
reg [1:0] s;
reg [3:0] ld_n;
always @(op or c_n) begin
s [1] <= op[1];
s [0] <= op[0] | op[3];
ld_n[0] <= op[2] | op[3];
ld_n[1] <= op[3] | ~(op[2] & 1 & 1);
... |
tt07-finale_0125 | tt07-finale | KosugiSubaru-tt07-td4cpu | task_ff_1bit | tt_um_TD4_Assy_KosugiSubaru | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_TD4_Assy_KosugiSubaru (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... | module ff_1bit(in, out, clk, rst, pr);
input in;
input clk, rst, pr;
output out;
reg out;
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
out <= 0;
end else begin
if (pr == 1'b0) begin
out <= 1;
end else begin
... |
tt07-finale_0126 | tt07-finale | KosugiSubaru-tt07-td4cpu | task_pc | tt_um_TD4_Assy_KosugiSubaru | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_TD4_Assy_KosugiSubaru (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... | module pc(in, out, ld, clk, rst, co);
input [3:0] in;
input ld, clk, rst;
output [3:0] out;
output co;
reg [3:0] out;
reg co;
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
out <= 4'b0000;
co <= 1'b0;
end else if (out == 4'b1111) be... |
tt07-finale_0127 | tt07-finale | KosugiSubaru-tt07-td4cpu | task_register_ff_4bit | tt_um_TD4_Assy_KosugiSubaru | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_TD4_Assy_KosugiSubaru (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... | module register_ff_4bit(in, out, ld, clk, rst);
input [3:0] in;
input ld, clk, rst;
output [3:0] out;
reg [3:0] out;
always @(posedge clk or negedge rst) begin
if (rst ==1'b0) begin
out <= 4'b0000;
end else begin
if (ld == 1'b1) begin
out <= ... |
tt07-finale_0128 | tt07-finale | KosugiSubaru-tt07-td4cpu | task_selector | tt_um_TD4_Assy_KosugiSubaru | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_TD4_Assy_KosugiSubaru (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... | module selector(in_a, in_b, in_c, in_d, s, out);
input [3:0] in_a, in_b, in_c, in_d;
input [1:0] s;
output [3:0] out;
reg [3:0] out;
always @(in_a or in_b or in_c or in_d or s) begin
case (s)
2'b00: out <= in_a;
2'b01: out <= in_b;
2'b10: out <= in_c;
... |
tt07-finale_0129 | tt07-finale | KosugiSubaru-tt07-td4cpu | task_tt_um_TD4_Assy_KosugiSubaru | tt_um_TD4_Assy_KosugiSubaru | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module tt_um_TD4_Assy_KosugiSubaru (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... | module tt_um_TD4_Assy_KosugiSubaru (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... |
tt07-finale_0130 | tt07-finale | NelsonSalvadorPinilla-tt07-PS_PWM_Modulator | task_Comparator | tt_um_PS_PWM | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Design Name: Top
// Module Name: Top
// Project Name: TT05 Modulacion PS-PWM para 3L-FCC
//////////////////////////////////////////////////////////////////////////////////
module tt_um_PS_PWM(
input wire [... | module Comparator(in1, in2, comparison);
parameter WIDTH_IN1 = 6;
parameter WIDTH_IN2 = 6;
input [WIDTH_IN1-1:0] in1;
input [WIDTH_IN2-1:0] in2;
output comparison;
reg comparison;
always @ (in1 or in2)
begin
comparison = (in1 >= in2);
end
endmodule |
tt07-finale_0131 | tt07-finale | NelsonSalvadorPinilla-tt07-PS_PWM_Modulator | task_Dead_Time_Generator | tt_um_PS_PWM | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Design Name: Top
// Module Name: Top
// Project Name: TT05 Modulacion PS-PWM para 3L-FCC
//////////////////////////////////////////////////////////////////////////////////
module tt_um_PS_PWM(
input wire [... | module Dead_Time_Generator(clk, dt, gi, go);
(* clock_signal = "yes" *)
input clk; //Reloj principal de 150MHz
input [4:0] dt; //Configuracion de tiempos muertos
input gi; //Senal a retardar (tiempo muerto)
output reg go; //Senal retarda... |
tt07-finale_0132 | tt07-finale | NelsonSalvadorPinilla-tt07-PS_PWM_Modulator | task_Shift_Register | tt_um_PS_PWM | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Design Name: Top
// Module Name: Top
// Project Name: TT05 Modulacion PS-PWM para 3L-FCC
//////////////////////////////////////////////////////////////////////////////////
module tt_um_PS_PWM(
input wire [... | module Shift_Register(
input wire CLK_SR,
input wire RST,
input wire data_in,
output wire [10:0] data_out
);
reg [10:0] internal_data [0:10];
reg [3:0] shift_state;
integer i;
always @(posedge CLK_SR or posedge RST) begin
if (RST) begin
// Reiniciar todas las variables internas a 0 cuando ... |
tt07-finale_0133 | tt07-finale | NelsonSalvadorPinilla-tt07-PS_PWM_Modulator | task_tt_um_PS_PWM | tt_um_PS_PWM | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Design Name: Top
// Module Name: Top
// Project Name: TT05 Modulacion PS-PWM para 3L-FCC
//////////////////////////////////////////////////////////////////////////////////
module tt_um_PS_PWM(
input wire [... | module tt_um_PS_PWM(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
in... |
tt07-finale_0134 | tt07-finale | Revenantx86-tt07-tinytpu | task_tt_um_revenantx86_tinytpu | tt_um_revenantx86_tinytpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_revenantx86_tinytpu
(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_... | module tt_um_revenantx86_tinytpu
(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1... |
tt07-finale_0135 | tt07-finale | Santeep-TT_UM_SERDES | task_decoder_10b_8b | tt_um_serdes | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_serdes (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module decoder_10b_8b(
input clk,
input rst_n,
input [9:0] data_10b_in,
input par_en,
output reg [7:0] data_8b_out
);
reg [2:0] temp_3b;
reg [4:0] temp_5b;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
... |
tt07-finale_0136 | tt07-finale | Santeep-TT_UM_SERDES | task_encoder_8b_10b | tt_um_serdes | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_serdes (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module encoder_8b_10b(
input clk,
input rst_n,
input [7:0] data_8b_in,
input ser_en,
output reg[9:0] data_10b_out
);
reg [3:0] temp_4b;
reg [5:0] temp_6b;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
... |
tt07-finale_0137 | tt07-finale | Santeep-TT_UM_SERDES | task_latch_10bit | tt_um_serdes | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_serdes (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module latch_10bit(
input clk,
input rst_n,
input [9:0] data_10b_in,
input data_en,
output reg [9:0] data_10b_out
);
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_10b_out <= 10'h00;
end
else begin
... |
tt07-finale_0138 | tt07-finale | Santeep-TT_UM_SERDES | task_latch_8bit | tt_um_serdes | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_serdes (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module latch_8bit(
input clk,
input rst_n,
input [7:0] data_8b_in,
input data_en,
output reg [7:0] data_8b_out
);
always @ ( posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_8b_out <= 8'h00;
end
else begin
... |
tt07-finale_0139 | tt07-finale | Santeep-TT_UM_SERDES | task_piso_10bit | tt_um_serdes | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_serdes (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module piso_10bit(
input clk,
input rst_n,
input [9:0] par_in,
input load_en,
output reg ser_out
);
reg [9:0] shift_reg;
always @(posedge clk) begin
if (!rst_n) begin
shift_reg <= 10'b0000000000;
end
else beg... |
tt07-finale_0140 | tt07-finale | Santeep-TT_UM_SERDES | task_serdes_top | tt_um_serdes | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_serdes (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module serdes_top(
input clk,
input rst_n,
input data_en,
input ser_in,
input par_en,
input ser_en,
output wire ser_out,
output wire [7:0] data_out,
input [7:0] data_8b_in
);
// Serializer module
wire [7... |
tt07-finale_0141 | tt07-finale | Santeep-TT_UM_SERDES | task_sipo_10bit | tt_um_serdes | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_serdes (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module sipo_10bit(
input clk,
input rst_n,
input ser_in,
input shift_en,
output reg [9:0] par_out
);
reg [9:0] shift_reg;
always @ (posedge clk)begin
if (!rst_n) begin
shift_reg <= 10'b0000000000;
end
else... |
tt07-finale_0142 | tt07-finale | Santeep-TT_UM_SERDES | task_tt_um_serdes | tt_um_serdes | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_serdes (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module tt_um_serdes (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
i... |
tt07-finale_0143 | tt07-finale | TinyTapeout-tt07-dvd-screensaver | task_bitmap_rom | tt_um_tinytapeout_dvd_screensaver | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Author: Uri Shaked
*/
`default_nettype none
parameter LOGO_SIZE = 128; // Size of the logo in pixels
parameter DISPLAY_WIDTH = 640; // VGA display width
parameter DISPLAY_HEIGHT = 480; // VGA display height
`define COLOR_WHITE 3'... | module bitmap_rom (
input wire [6:0] x,
input wire [6:0] y,
output wire pixel
);
reg [7:0] mem[2047:0];
initial begin
mem[0] = 8'h00;
mem[1] = 8'h00;
mem[2] = 8'h00;
mem[3] = 8'h00;
mem[4] = 8'h00;
mem[5] = 8'h00;
mem[6] = 8'h00;
mem[7] = 8'h00;
mem[8] = 8'h00;
m... |
tt07-finale_0144 | tt07-finale | TinyTapeout-tt07-dvd-screensaver | task_palette | tt_um_tinytapeout_dvd_screensaver | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Author: Uri Shaked
*/
`default_nettype none
parameter LOGO_SIZE = 128; // Size of the logo in pixels
parameter DISPLAY_WIDTH = 640; // VGA display width
parameter DISPLAY_HEIGHT = 480; // VGA display height
`define COLOR_WHITE 3'... | module palette (
input wire [2:0] color_index,
output wire [5:0] rrggbb
);
reg [5:0] palette[7:0];
initial begin
palette[0] = 6'b001011; // cyan
palette[1] = 6'b110110; // pink
palette[2] = 6'b101101; // green
palette[3] = 6'b111000; // orange
palette[4] = 6'b110011; // purple
... |
tt07-finale_0145 | tt07-finale | TinyTapeout-tt07-dvd-screensaver | task_tt_um_tinytapeout_dvd_screensaver | tt_um_tinytapeout_dvd_screensaver | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Author: Uri Shaked
*/
`default_nettype none
parameter LOGO_SIZE = 128; // Size of the logo in pixels
parameter DISPLAY_WIDTH = 640; // VGA display width
parameter DISPLAY_HEIGHT = 480; // VGA display height
`define COLOR_WHITE 3'... | module tt_um_tinytapeout_dvd_screensaver (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=i... |
tt07-finale_0146 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_DSR_left_N_S | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module DSR_left_N_S(a,b,c);
parameter N=16;
parameter S=4;
input [N-1:0] a;
input [S-1:0] b;
output [N-1:0] c;
wire [N-1:0] tmp [S-1:0];
assign tmp[0] = b[0] ? a << 7'd1 : a;
genvar i;
generate
for (i=1; i<S; i=i+1)begin:loop_blk
assign tmp[i] = b[i] ? tmp[i-1] << 2**i : t... |
tt07-finale_0147 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_LOD | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module LOD (in, out, vld);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
output vld;
generate
if (N ... |
tt07-finale_0148 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_LOD_N | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module LOD_N (in, out);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
wire vld;
LOD #(.N(N)) l1 (in, out, vld);
endm... |
tt07-finale_0149 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_a_abs_regime | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module a_abs_regime (rc, regime, regime_N);
parameter N = 10;
input rc;
input [N-1:0] regime;
output [N:0] regime_N;
assign regime_N = rc ? {1'b0,regime} : -{1'b0,regime};
endmodule |
tt07-finale_0150 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_a_add_N_in | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module a_add_N_in (a,b,c);
parameter N=10;
input [N:0] a,b;
output [N:0] c;
assign c = a + b;
endmodule |
tt07-finale_0151 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_a_add_sub_N | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module a_add_sub_N (op,a,b,c);
parameter N=10;
input op;
input [N-1:0] a,b;
output [N:0] c;
wire [N:0] c_add, c_sub;
a_add_N #(.N(N)) a11 (a,b,c_add);
a_sub_N #(.N(N)) s11 (a,b,c_sub);
assign c = op ? c_add : c_sub;
endmodule |
tt07-finale_0152 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_a_reg_exp_op | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module a_reg_exp_op (exp_o, e_o, r_o);
parameter ES=3;
parameter Bs=5;
input [ES+Bs:0] exp_o;
output [ES-1:0] e_o;
output [Bs-1:0] r_o;
assign e_o = exp_o[ES-1:0];
wire [ES+Bs:0] exp_oN_tmp;
conv_2c #(.N(ES+Bs)) uut_conv_2c1 (~exp_o[ES+Bs:0],exp_oN_tmp);
wire [ES+Bs:0] exp_oN = exp_o[ES+Bs] ? exp_oN_tmp[ES+Bs:0] : ex... |
tt07-finale_0153 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_a_sub_N | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module a_sub_N (a,b,c);
parameter N=10;
input [N-1:0] a,b;
output [N:0] c;
wire [N:0] ain = {1'b0,a};
wire [N:0] bin = {1'b0,b};
a_sub_N_in #(.N(N)) s1 (ain,bin,c);
endmodule |
tt07-finale_0154 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_add_1 | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module add_1 (a,mant_ovf,c);
parameter N=10;
input [N:0] a;
input mant_ovf;
output [N:0] c;
assign c = a + mant_ovf;
endmodule |
tt07-finale_0155 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_conv_2c | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module conv_2c (a,c);
parameter N=10;
input [N:0] a;
output [N:0] c;
assign c = a + 1'b1;
endmodule |
tt07-finale_0156 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_data_extract_v1 | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module data_extract_v1(in, rc, regime, exp, mant);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N=16;
parameter Bs=log2(N);
parameter ES = 2;
input [N-1:0] in;
output rc;
output [Bs-1:0] regime;
o... |
tt07-finale_0157 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_dda | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module dda (
input clk, // Clock
input rst_n, // Reset (active low)
output [N-1:0] x,y, // Dynamical system state variables
input [N-1:0] icx, icy, // Initial conditions
input [N-1:0] mu // Van-der-Pol parameter
);
// Posit parameters
parameter N = 16;
parameter ES = 1;
// Multiplications
wire [N-... |
tt07-finale_0158 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_euler_integrator | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module euler_integrator(out, funct, clk, rst_n, ic);
parameter N = 16;
parameter ES = 1;
input clk, rst_n;
output [N-1:0] out; // state variable
input [N-1:0] funct; // the dV/dt function
input [N-1:0] ic; // initial condition
wire [N-1:0] out, v1new;
reg [N-1:0] v1;
wire [N-1:0] out_mult;
// compute new... |
tt07-finale_0159 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_m_add_N | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module m_add_N (a,b,c);
parameter N=10;
input [N-1:0] a,b;
output [N:0] c;
assign c = {1'b0,a} + {1'b0,b};
endmodule |
tt07-finale_0160 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_m_add_N_Cin | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module m_add_N_Cin (a,b,cin,c);
parameter N=10;
input [N:0] a,b;
input cin;
output [N:0] c;
assign c = a + b + cin;
endmodule |
tt07-finale_0161 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_m_reg_exp_op | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module m_reg_exp_op (exp_o, e_o, r_o);
parameter ES=3;
parameter Bs=5;
input [ES+Bs+1:0] exp_o;
output [ES-1:0] e_o;
output [Bs:0] r_o;
assign e_o = exp_o[ES-1:0];
wire [ES+Bs:0] exp_oN_tmp;
conv_2c #(.N(ES+Bs)) uut_conv_2c1 (~exp_o[ES+Bs:0],exp_oN_tmp);
wire [ES+Bs:0] exp_oN = exp_o[ES+Bs+1] ? exp_oN_tmp[ES+Bs:0] : ... |
tt07-finale_0162 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_posit_add | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module posit_add (in1, in2, out);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter ES = 1;
input [N-1:0] in1, in2;
output [N-1:0] out;
wire inf, zero;
wire... |
tt07-finale_0163 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_posit_dt_mult | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module posit_dt_mult(in1, out);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter ES = 1;
input [N-1:0] in1;
output [N-1:0] out;
wire s1 = in1[N-1];
wire s2... |
tt07-finale_0164 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_posit_mult | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module posit_mult(in1, in2, out);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter ES = 1;
input [N-1:0] in1, in2;
output [N-1:0] out;
wire inf, zero;
wire... |
tt07-finale_0165 | tt07-finale | adonairc-tt07-dda-van-der-pol | task_tt_um_adonairc_dda | tt_um_adonairc_dda | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Adonai Cruz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module tt_um_adonairc_dda (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)... |
tt07-finale_0166 | tt07-finale | afasolino-tt06_posit | task_BNE_16b | tt_um_afasolino | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
Based on paper:
R. Murillo, A. A. Del Barrio and G. Botella, "Customized Posit Adders and Multipliers using the FloPoCo Core Generator," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5,
doi: 10.1109/ISCAS45731.2020.9180771.
*/
module add #(parameter N=16) (
input wire i_s_1,
... | module BNE_16b(
input wire [3:0] a,
output wire Q,
output wire [1:0] y
);
assign Q = a[0] & a[1] & a[2] & a[3];
assign y[1] = a[0] & a[1];
assign y[0] = a[0] & (!a[1] | a[2] );
endmodule |
tt07-finale_0167 | tt07-finale | afasolino-tt06_posit | task_Fixed16toPosit16 | tt_um_afasolino | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
Based on paper:
R. Murillo, A. A. Del Barrio and G. Botella, "Customized Posit Adders and Multipliers using the FloPoCo Core Generator," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5,
doi: 10.1109/ISCAS45731.2020.9180771.
*/
module add #(parameter N=16) (
input wire i_s_1,
... | module Fixed16toPosit16(
input [15:0] fixed_number_input,
output [3:0] regime_value,
output exponent,
output wire [11:0] mantissa,
output Q,
output sign
);
wire [15:0] fixed_number,fixed_numberaux, fixed_number_neg;
// 2's complement to extract value and s... |
tt07-finale_0168 | tt07-finale | afasolino-tt06_posit | task_LeadingZeroCounter_16b | tt_um_afasolino | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
Based on paper:
R. Murillo, A. A. Del Barrio and G. Botella, "Customized Posit Adders and Multipliers using the FloPoCo Core Generator," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5,
doi: 10.1109/ISCAS45731.2020.9180771.
*/
module add #(parameter N=16) (
input wire i_s_1,
... | module LeadingZeroCounter_16b(
input wire [15:0] x,
output wire [3:0] count,
output wire Q
);
wire [3:0] auxa;
wire [7:0] auxz;
wire [1:0] auxcount;
genvar k;
generate
for (k=0; k < 4; k=k+1)
begin: NLC_generation
NLC_16b NLC (.x(x[15-4*k : 12-4*k]),
.a(auxa[k]),
... |
tt07-finale_0169 | tt07-finale | afasolino-tt06_posit | task_Mux_LZC_16b | tt_um_afasolino | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
Based on paper:
R. Murillo, A. A. Del Barrio and G. Botella, "Customized Posit Adders and Multipliers using the FloPoCo Core Generator," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5,
doi: 10.1109/ISCAS45731.2020.9180771.
*/
module add #(parameter N=16) (
input wire i_s_1,
... | module Mux_LZC_16b(
input wire [1:0] i0 ,
input wire [1:0] i1 ,
input wire [1:0] i2 ,
input wire [1:0] i3 ,
input wire [1:0] s ,
output reg [1:0] o
);
always @(*)
case (s)
2'b00: o = i0;
2'b01: o = i1;
2'b10: o = i2;
2'b11: o = i3;
endcase
endmodule |
tt07-finale_0170 | tt07-finale | afasolino-tt06_posit | task_NLC_16b | tt_um_afasolino | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
Based on paper:
R. Murillo, A. A. Del Barrio and G. Botella, "Customized Posit Adders and Multipliers using the FloPoCo Core Generator," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5,
doi: 10.1109/ISCAS45731.2020.9180771.
*/
module add #(parameter N=16) (
input wire i_s_1,
... | module NLC_16b (
input wire [3:0] x, // Dedicated inputs
output wire a, // Dedicated inputs
output wire [1:0] z // Dedicated inputs
);
wire aprimo,z1,z0,aux1;
assign aprimo = x[3] | x[2] | x[1] | x[0];
assign a = ! aprimo;
assign z1 = x[3] | x[2];
assign z[1] = ! z1;
assign z0 = aux1 |... |
tt07-finale_0171 | tt07-finale | afasolino-tt06_posit | task_tt_um_afasolino | tt_um_afasolino | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
Based on paper:
R. Murillo, A. A. Del Barrio and G. Botella, "Customized Posit Adders and Multipliers using the FloPoCo Core Generator," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5,
doi: 10.1109/ISCAS45731.2020.9180771.
*/
module add #(parameter N=16) (
input wire i_s_1,
... | module tt_um_afasolino (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wir... |
tt07-finale_0172 | tt07-finale | aj-stein-nist-tt_stopwatch_project | task_tt_um_ajstein_stopwatch | tt_um_ajstein_stopwatch | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | //_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.14-2022/10/10-beta-Pro
//_\source top.tlv 36
//_\SV
// Include Tiny Tapeout Lab.
// Included URL: "https://raw.githubusercontent.com/os-fpga/Virtual-FPGA-Lab/35e36bd144fddd75495d4cbc01c4fc50ac5bde6f/tlv_lib/tiny_tapeout_lib.tlv"// Included URL: "https://... | module tt_um_ajstein_stopwatch (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
// The FPGA is based on TinyTapeout 3 which has no bidirectional I/Os (vs. TT6 for the ASIC).
input ... |
tt07-finale_0173 | tt07-finale | asinghani-tinywspr-tt07 | task_BitGenerator | tt_um_asinghani_tinywspr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Anish Singhani
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_asinghani_tinywspr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module BitGenerator (
clock,
reset,
io_config_in_valid,
io_config_in_bits,
io_start,
io_bit_out_ready,
io_bit_out_bits
);
input clock;
input reset;
input io_config_in_valid;
input [7:0] io_config_in_bits;
input io_start;
input io_bit_out_ready;
output wire [1:0] io_bit_out_bits;
wire _se_io_done;
wire _... |
tt07-finale_0174 | tt07-finale | asinghani-tinywspr-tt07 | task_StringEncoder | tt_um_asinghani_tinywspr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Anish Singhani
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_asinghani_tinywspr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module StringEncoder (
clock,
reset,
io_config_in_valid,
io_config_in_bits,
io_start,
io_done,
io_bit_out_valid,
io_bit_out_bits
);
input clock;
input reset;
input io_config_in_valid;
input [7:0] io_config_in_bits;
input io_start;
output wire io_done;
output wire io_bit_out_valid;
output wire io_bit_out... |
tt07-finale_0175 | tt07-finale | asinghani-tinywspr-tt07 | task_TopLevel | tt_um_asinghani_tinywspr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Anish Singhani
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_asinghani_tinywspr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module TopLevel (
clock,
reset,
io_config_bits_in,
io_config_valid_in,
io_config_start,
io_rf_start,
io_rf_out,
io_bit_out
);
input clock;
input reset;
input [7:0] io_config_bits_in;
input io_config_valid_in;
input io_config_start;
input io_rf_start;
output wire io_rf_out;
output wire [1:0] io_bit_out;
... |
tt07-finale_0176 | tt07-finale | asinghani-tinywspr-tt07 | task_tt_um_asinghani_tinywspr | tt_um_asinghani_tinywspr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Anish Singhani
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_asinghani_tinywspr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] u... | module tt_um_asinghani_tinywspr (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=o... |
tt07-finale_0177 | tt07-finale | barakhoffer-tt07-vga-snake | task_snake | tt_um_vga_snake | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Barak Hoffer
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_vga_snake (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, //... | module snake(clk, rst_n, x_px, y_px, rrggbb, left, right, up, down);
input clk;
input rst_n;
input [9:0] x_px;
input [9:0] y_px;
input left;
input right;
input up;
input down;
output wire [5:0] rrggbb;
localparam MAX_SIZE = 6;
reg [MAX_SIZE*10-1:0] snakeX = {(MAX_SIZE){10'd... |
tt07-finale_0178 | tt07-finale | barakhoffer-tt07-vga-snake | task_tt_um_vga_snake | tt_um_vga_snake | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Barak Hoffer
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_vga_snake (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, //... | module tt_um_vga_snake (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt07-finale_0179 | tt07-finale | cpacejo-adia_psu_seq_test | task_tt_um_adia_psu_seq_test | tt_um_adia_psu_seq_test | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Applied Invention, LLC
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_adia_psu_seq_test (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire ... | module tt_um_adia_psu_seq_test (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=ou... |
tt07-finale_0180 | tt07-finale | drburke3-FastMagnitudeComparator | task_comparator_bitslice | tt_um_drburke3_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`define default_netname none
// Begin Tiny Tapeout wrapper interface
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wir... | module comparator_bitslice(
input A,
input B,
input LT_in,
input EQ_in,
input GT_in,
output LT_out,
output EQ_out,
output GT_out
);
// original naive structural Verilog code as per RealDigital
// assign GT_out = ( A & ~B ) | (~(A ^ B) & GT_in);
// re-expressed in AND-INV form for o... |
tt07-finale_0181 | tt07-finale | drburke3-FastMagnitudeComparator | task_magnitude_comparator | tt_um_drburke3_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`define default_netname none
// Begin Tiny Tapeout wrapper interface
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wir... | module magnitude_comparator(
input [7:0] A,
input [7:0] B,
output LT_out,
output EQ_out,
output GT_out
);
wire [7:0] GT_internal;
wire [7:0] EQ_internal;
wire [7:0] LT_internal;
comparator_bitslice slice_0 (
.A(A[0]),
.B(B[0]),
.LT_in(1'b0),
.EQ_in(1'b1),
.GT_in(1'b0),
... |
tt07-finale_0182 | tt07-finale | ejfogleman-tt07-ef-smsdac8 | task_ef_lfsr20_8 | tt_um_ejfogleman_smsdac8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Eric Fogleman
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Blocks for fully-segmented mismatch shaping encoder
* from SEGMENTED MISMATCH-SHAPING D/A CONVERSION,
* Fishov, Fogleman, Siragusa, Galton
* 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
*/
/* verilator ... | module ef_lfsr20_8 (
input i_clk,
input i_rst_b,
input i_en,
output wire [7:0] o_r );
reg [19:0] q;
assign o_r[7:0] = q[8:1];
always @( posedge i_clk, negedge i_rst_b ) begin
if( ~i_rst_b ) begin
q[19:1] <= 19'b0;
q[0] <= 1'b1;
end
else begin
if ( i_en ) begin
// jumps 8 states per clo... |
tt07-finale_0183 | tt07-finale | ejfogleman-tt07-ef-smsdac8 | task_ef_smsdac8_mse | tt_um_ejfogleman_smsdac8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Eric Fogleman
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Blocks for fully-segmented mismatch shaping encoder
* from SEGMENTED MISMATCH-SHAPING D/A CONVERSION,
* Fishov, Fogleman, Siragusa, Galton
* 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
*/
/* verilator ... | module ef_smsdac8_mse (
input i_clk,
input i_rst_b,
input i_en,
input [7:0] i_x,
input i_xc,
input [7:0] i_r,
output [13:0] o_y ); // y64[1:0], y32[1:0], ..., y1[1;0]
// 8 layers: input 7, output 0
// elements numbered top to bottom.
// signals and instances use layer, element notation:
// u_s70 is 0t... |
tt07-finale_0184 | tt07-finale | ejfogleman-tt07-ef-smsdac8 | task_ef_smsdac8_top | tt_um_ejfogleman_smsdac8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Eric Fogleman
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Blocks for fully-segmented mismatch shaping encoder
* from SEGMENTED MISMATCH-SHAPING D/A CONVERSION,
* Fishov, Fogleman, Siragusa, Galton
* 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
*/
/* verilator ... | module ef_smsdac8_top(
input i_clk,
input i_rst_b,
input i_en_enc,
input i_en_dith,
input [7:0] i_x,
output wire [13:0] o_y ); // y64[1:0], y32[1:0], ..., y1[1;0]
wire [7:0] x_sync1, x_sync2; // input data synchronizer
wire [7:0] r; // random dither bits
wire [13:0] y; // e... |
tt07-finale_0185 | tt07-finale | ejfogleman-tt07-ef-smsdac8 | task_ef_smsdac_mse_sb_sm | tt_um_ejfogleman_smsdac8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Eric Fogleman
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Blocks for fully-segmented mismatch shaping encoder
* from SEGMENTED MISMATCH-SHAPING D/A CONVERSION,
* Fishov, Fogleman, Siragusa, Galton
* 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
*/
/* verilator ... | module ef_smsdac_mse_sb_sm(
input i_clk,
input i_rst_b,
input i_odd,
input i_r,
input i_en,
output wire o_q );
// switching sequence; update only on odd inputs
// en == 1'b0 stops mismatch shaping (static encoder)
reg [1:0] q;
wire [1:0] q_d; // next state info
assign q_d[1] = (i_en & i_odd) ? ~q[1]... |
tt07-finale_0186 | tt07-finale | ejfogleman-tt07-ef-smsdac8 | task_ef_smsdac_mse_seg_sb | tt_um_ejfogleman_smsdac8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Eric Fogleman
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Blocks for fully-segmented mismatch shaping encoder
* from SEGMENTED MISMATCH-SHAPING D/A CONVERSION,
* Fishov, Fogleman, Siragusa, Galton
* 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
*/
/* verilator ... | module ef_smsdac_mse_seg_sb (
input i_clk,
input i_rst_b,
input i_r,
input i_en,
input i_x,
input i_xc,
output wire [1:0] o_y,
output wire o_yc );
wire odd = i_x ^ i_xc; // input parity
wire q; // switching sequence
// "carry" output (lsb weight); round up/down on odd input
assign o_yc = odd ? ... |
tt07-finale_0187 | tt07-finale | ejfogleman-tt07-ef-smsdac8 | task_tt_um_ejfogleman_smsdac8 | tt_um_ejfogleman_smsdac8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Eric Fogleman
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Blocks for fully-segmented mismatch shaping encoder
* from SEGMENTED MISMATCH-SHAPING D/A CONVERSION,
* Fishov, Fogleman, Siragusa, Galton
* 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
*/
/* verilator ... | module tt_um_ejfogleman_smsdac8 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
// verilator lint_off UNUSEDSIGNAL
input wire [7:0] uio_in, // IOs: Input path
// verilator lint_off UNUSEDSIGNAL
output wire [7:0] uio_out, // IOs: Output path
... |
tt07-finale_0188 | tt07-finale | ender110-tt07-clock | task_day_of_month | tt_um_ender_clock | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
/* verilator lint_off UNUSEDSIGNAL */
`default_nettype none
/* verilator lint_off WIDTHTRUNC */
module tt_um_ender_clock (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wi... | module day_of_month(
input wire [3:0]month,
output wire[4:0] day_this_month
);
assign day_this_month=month==1?5'd31:month==2?5'd28:month==3?5'd31:month==4?5'd30:month==5?5'd31:month==6?5'd30:month==7?5'd31:month==8?5'd31:month==9?5'd30:month==10?5'd31:month==11?5'd30:5'd31;
endmodule |
tt07-finale_0189 | tt07-finale | ender110-tt07-clock | task_key | tt_um_ender_clock | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
/* verilator lint_off UNUSEDSIGNAL */
`default_nettype none
/* verilator lint_off WIDTHTRUNC */
module tt_um_ender_clock (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wi... | module key(
input clock,input reset,input time_flag,
input key_in,output key_out
);
reg [3:0]key_filter;
always @(posedge clock or negedge reset)
begin
if(reset==1'd0)
begin
key_filter<=4'b1111;
end
else
begin
if(time_flag==1)
begin
key_filter<={key_... |
tt07-finale_0190 | tt07-finale | ender110-tt07-clock | task_segment_code | tt_um_ender_clock | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
/* verilator lint_off UNUSEDSIGNAL */
`default_nettype none
/* verilator lint_off WIDTHTRUNC */
module tt_um_ender_clock (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wi... | module segment_code(
input wire [3:0]number,output wire [6:0]code
);
assign code=number==0?7'h3f:number==1?7'h06:number==2?7'h5b:number==3?7'h4f:number==4?7'h66:number==5?7'h6d:number==6?7'h7d:number==7?7'h07:number==8?7'h7f:number==9?7'h6f:7'h0;
endmodule |
tt07-finale_0191 | tt07-finale | ender110-tt07-clock | task_segment_show | tt_um_ender_clock | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
/* verilator lint_off UNUSEDSIGNAL */
`default_nettype none
/* verilator lint_off WIDTHTRUNC */
module tt_um_ender_clock (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wi... | module segment_show(input wire clock,input wire reset,input wire [11:0]data_show,
input wire [2:0]byte_status,output wire [3:0]bytee,output wire [6:0]segment,input wire [3:0]segment_byte_control);
wire [5:0]data_showing;
assign data_showing=byte_status==0?data_show[5:0]:byte_status==2?data_show[5:0]:byte_status==4?da... |
tt07-finale_0192 | tt07-finale | ender110-tt07-clock | task_tt_um_ender_clock | tt_um_ender_clock | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
/* verilator lint_off UNUSEDSIGNAL */
`default_nettype none
/* verilator lint_off WIDTHTRUNC */
module tt_um_ender_clock (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wi... | module tt_um_ender_clock (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt07-finale_0193 | tt07-finale | jasonkaufmann-tt07-fulladder8bit | task_fulladder | tt_um_8bitadder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Jason Kaufmann
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_8bitadder (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module fulladder(input wire cin,
input wire a,
input wire b,
output wire s,
output wire cout);
wire s_tmp, cout_tmp1, cout_tmp2;
halfadder h0(.a(a), .b(b), .s(s_tmp), .cout(cout_tmp1));
halfadder h1(.a(s_tmp), .b(cin), .s(s), .cout(cout_tm... |
tt07-finale_0194 | tt07-finale | jasonkaufmann-tt07-fulladder8bit | task_halfadder | tt_um_8bitadder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Jason Kaufmann
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_8bitadder (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module halfadder(input wire a,
input wire b,
output wire s,
output wire cout);
assign s = a ^ b;
assign cout = a & b;
endmodule |
tt07-finale_0195 | tt07-finale | jasonkaufmann-tt07-fulladder8bit | task_rca8 | tt_um_8bitadder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Jason Kaufmann
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_8bitadder (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module rca8(input wire [7:0] A,
input wire [7:0] B,
input wire cin,
output wire [7:0] SUM,
output wire cout);
wire [7:0] carry;
fulladder fa0 (.cin(cin), .a(A[0]), .b(B[0]), .s(SUM[0]), .cout(carry[0]));
fulladder fa1 (.cin(carry[0]), .a(A[... |
tt07-finale_0196 | tt07-finale | jasonkaufmann-tt07-fulladder8bit | task_tt_um_8bitadder | tt_um_8bitadder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Jason Kaufmann
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_8bitadder (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module tt_um_8bitadder (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt07-finale_0197 | tt07-finale | jleightcap-tt07 | task_Fractran | tt_um_jleightcap | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Jack Leightcap
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_jleightcap (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module Fractran
( // Inputs
input [7:0] accumulator
, input [7:0] fraction
, input clk // clock
, input rst // reset
, input en // enable
// Outputs
, output wire [7:0] degree
, output wire we
, output wire halt
, output wire [5:0] count
);
// src/Fractran.hs:... |
tt07-finale_0198 | tt07-finale | jleightcap-tt07 | task_tt_um_jleightcap | tt_um_jleightcap | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Jack Leightcap
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_jleightcap (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, ... | module tt_um_jleightcap (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt07-finale_0199 | tt07-finale | leeja-j-router_tinytapeout | task_router_fifo | tt_um_router | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_router (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module router_fifo(clock,resetn,soft_reset,write_enb,read_enb,
lfd_state,data_in,full,empty,data_out);
input clock,resetn,soft_reset;
input write_enb,read_enb,lfd_state;
input [2:0]data_in;
output reg [2:0] data_out;
output full,empty;
reg [4:0] rd_pointer,wr_pointer;
reg [6:0]... |
tt07-finale_0200 | tt07-finale | leeja-j-router_tinytapeout | task_router_fsm | tt_um_router | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_router (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module router_fsm(clock,resetn,pkt_valid,data_in,fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_2,
soft_reset_0,soft_reset_1,soft_reset_2,parity_done,low_packet_valid,
write_enb_reg,detect_add,ld_state,laf_state,lfd_state,full_state,rst_int_reg,busy);
input clock,resetn,pkt_valid,fi... |
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